Non-inverting Audio Buffer Distortion - what's the cause?

[ssashton]

Hello,

I have built the following circuit to drive my ADC.


(click to enlarge)

I started with using only U2.1 and U2.2. Feeding the audio signal direct to C3. The distortion and noise is very low (red trace). However, I wanted to buffer the input impedance as 5K is rather low, so I added U1.1.  The circuit does work, but distortion is raised by 10dB as the Green trace below.



I then tried adding a feedback network on U1.1 of 5K1 series and 5K1 to ground. Gain was increased by 6dB, yet the distortion fell to the same as the direct connection. No image as the result was identical to the red trace only with a bit more noise.

So I then tried simply a 20K series resistor and 100pF bypass cap in the feedback (nothing to ground). I got unity gain now with lower distortion, yet still not as low as the direct connection or 6dB gain arrangement.



I tried 100K series resistance with 100pF bypass and distortion increased again.



I did also try 5K1 (to match the bias resistor) and 150R (to match source resistance) but I only saw very small differences from the initial result.

What is the mechanism of distortion here and why does a series feedback resistor and especially a shunt feedback network help to reduce it?

Ideally, I want low distortion with unity gain for low noise. Using 6dB gain and then attenuation seems silly (plus my bias voltage is limited).

[MasterT]

Things to suspect:
1. Oscillation,  try to remove C1, or put 2 R2 and set C1 in between
2. Input bias, if it affects following stages, impedance must be very low since THD is quite low on dB scale -100 or something this dictates input_bias be below 5k / 10^5 = 50 milliOhms , or even 5 mOhm if -120dBc is objective.

[TimFox]

General point, maybe applicable to your situation.
An inverting op amp circuit has almost no common-mode voltage at the op amp input.
A non-inverting circuit usually has the full input voltage as common-mode, and the op amp will respond to it in a non-linear manner.
Also, the input current of the op amp will vary non-linearly with cm voltage, creating an actual non-linear voltage component at the op amp input when flowing through the source and feedback impedances.
Of course, the magnitude of these cm effects is a quantitative effect.
A complicated method to reduce this is to “bootstrap” the op amp power terminals with another op amp to reduce the cm voltage seen by the signal op amp.

[ssashton]

I increased thr bias voltage and the issue went away. I'm not sure why the voltage follower configuration needs a higher bias voltage than the inverting stages??

The result is still very slightly higher distortion, but nothing like what I was seeing earlier. I have read that voltage followers / non-inverting configurations do have higher diatortion than inverting configurations. Rather than try to explain why myself I'll link this topic - https://www.diyaudio.com/community/threads/opamp-inverting-input-sounds-better.6558/#:~:text=Well%20known%20phenomenon%20%3A%20using%20non,rejection%20ratio%20at%20the%20inputs

[coppice]

I can't see where INPUT_BIAS comes from, but it sure connects a lot of things together. My guess is its poorly decoupled, and causing crosstalk in unfortunate ways. Also, R1 seems to slam 5.1k ohms across the input, but you said you want to achieve a much higher input impedance than 5k ohms. How is that supposed to work?

[ssashton]

Sorry to Master T and Tim Fox, I did not see your messages for aome reason before I sent my initial follow-up. My link explains what Tim Fox said about CM voltage at the inputs.

I did try to buffer the input bias feeding the non-inverting stage U1.1 using U1.2, so that it is isolated from the bias feeding the two inverting stages. It did not improve matters. The bias is clean, low impedance and decoupled by 1uf 0603 and 10uf tant. I get -119dB noise floor with the inverting stages only.

I had also used 20K on the non-inverting input buffer in the beginning, as I was aiming for a higher input impedance, but I switched it to 5k1 so it matched the load of the inverting stages, to see if the load on my source was affecting things. It did not.

So for some reason the bias voltage is enough to run the inverting stages nicely, but the non-inverting needs a higher bias. That also explains why it worked better at gain=2 since the bias was doubled. The small remaining distortion increase after upping the bias I guess is the CM issue Tim Fox mentioned.

It's a shame, if I use the non inverting input buffer I can have higher input impedance as well as drop the resistor values around the inverting stages to get lower noise floor. But distortion slightly increases. Doesn't really seem worth it, but a good learning opertunity about common mode voltage distortion!

Thanks for all your inputs on this!

[nfmax]

In many cases, the inputs of an IC opamp are circuit nodes isolated from the (usually negative) supply rail by reverse-biased PN junctions. These junctions have a capacitance which forms part of the common-mode input capacitance of the IC. The actual value of the capacitance will vary with the width of the depletion layer, which in turn depends on the reverse bias voltage. Varying this voltage will vary the capacitance: in a non-inverting circuit the input signal will do this.

This results in an impedance to ground that varies with signal, causing a non-harmonic (distortion) current to flow: this does not happen in a non-inverting circuit. Result: distortion!

You can reduce the effect in many ways, for example by reducing the source impedance, placing an impedance in parallel with the input capacitance ( so that the voltage modulation of the depletion capacitance is a smaller part of the total current), or by increasing the DC bias voltage, moving the operating point to a less steeply sloping part of the C-V curve. In extreme cases, bootstrapping the supplies effectively eliminates the variation in common-mode voltage.

[MasterT]

Let's me try ones more to re-interpret:
"Input bias, if it affects following stages, impedance must be very low since THD is quite low on dB scale -100 or something this dictates input_bias be below 5k / 10^5 = 50 milliOhms , or even 5 mOhm if -120dBc is objective."

I mean, that buffer U.1.2 has not zero output inpedance. So current injected (input signal voltage via R1) to output generates small voltage, that would flow to other inverting stages And change theirs CM voltages. Secondly, U.1.2 operates at worst condition from zero-cross point of view, so it's not just has impedance (10-50 mOhms depends on freq.) but this impedance is unlinear. Two options to remedy situation:
 - load U.1.2 by dummy resistor to ground, essentially converting output stage into pure class A. 2k ohm 'd be fine.
- not use bias for first stage U.1.1. just use couple more resistors to create "own" bias network, not sharreble with anything else, since R1 is only interference element for other stages.

[magic]

What is that INPUT_BIAS exactly and why is it shared with the inverting stages if everything is AC coupled and there is no need for a common DC level?

It does sound like common mode distortion. There is distortion in the sense of varying input offset voltage and distortion in the sense of varying input bias current. Some "magic" value of source resistance on IN+ or IN- may result in partial cancellation, but unclear how reliable it is.

If increasing INPUT_BIAS helps, you are probably simply running too close to GND and the input pair (PNP) saturates or bias cancellation gets wonky. Or both. As for Cbc of the input PNPs, it ought to actually decrease in magnitude and in slope close to GND so that's good. But performance isn't good, so other factors must be dominating.

[TimFox]

In many cases, the inputs of an IC opamp are circuit nodes isolated from the (usually negative) supply rail by reverse-biased PN junctions. These junctions have a capacitance which forms part of the common-mode input capacitance of the IC. The actual value of the capacitance will vary with the width of the depletion layer, which in turn depends on the reverse bias voltage. Varying this voltage will vary the capacitance: in a non-inverting circuit the input signal will do this.

This results in an impedance to ground that varies with signal, causing a non-harmonic (distortion) current to flow: this does not happen in a non-inverting circuit. Result: distortion!

You can reduce the effect in many ways, for example by reducing the source impedance, placing an impedance in parallel with the input capacitance ( so that the voltage modulation of the depletion capacitance is a smaller part of the total current), or by increasing the DC bias voltage, moving the operating point to a less steeply sloping part of the C-V curve. In extreme cases, bootstrapping the supplies effectively eliminates the variation in common-mode voltage.

Another example of a non-linear input current (causing distortion) is for a BJT input amplifier, where the Early effect makes the base current a (not very strong) function of collector-base voltage.
The CM voltage will vary the collector-base voltage, since the collector usually goes to a roughly constant voltage node.

[ssashton]

What is 'Input Bias'? It is the 'V Ref' output of the ADC, which is ED9821Q. It is 3V, generated by an LDO internal to the ADC. Decoupled at the output and near the opamps. The output impedance I measured as 0.68 ohms. (Edit: that is DC. At AC the decoupling will provide very low impedance to ground.)

The bias should be enough for the 1v rms Input signal not to clip and with only the inverting stages all is good.

The bias is needed for two reasons. I'm running single rail +12v. The ADC needs Input bias.

Master T. I understand your point. You mean there could be crosstalk between each gain stage via the bias feed. When I said that I used U1.2 as a buffer for the bias, it is only for feeding U1.1. While U2.1 and U2.2 where fed from the original supply. So the non-inverting and inverting bias was isolated, but the distortion remained.

I'm still pondering why the distortion went down the most when I set the non-inverting stage to gain=2. This gives a bias at the output of 6v, but both inputs remain at 3v. Similarly, simply increasing the 'Input bias' to 6v also worked just as well. So I'm thinking the primary cause of distortion is to do with something other than the input nodes of the opamp. Is there any reason a non-inverting stage can't swing the output as close to the negative rail as comfortably an inverting stage?

[ssashton]

So I think I can answer my own question. Yes there is a good reason why an inverting stage is able to swing closer to the negative rail than a non-inverting one.

In a non-inverting stage, I apply a DC bias to the non-inverting input. The signal is also applied here, so when the signal swings negative this is super-imposed on the DC bias and the op-amp input gets close to the negative rail where it can not operate well.

On the other hand, with an inverting stage, the DC bias is applied on the non-inverting pin while the signal is applied on the inverting pin. The op-amp will adjust it's output to keep the inverting pin / node at the same voltage as the non-inverting one. So even when the input signal applied to the inverting pin tries to swing negative, the opamp's output will hold it at the same DC voltage as the non-inverting input. Thus neither input goes close to the negative rail and remain in their linear region. 

Then again, setting the gain of the non-inverting stage to 2x does not change the voltage at the input pins so.. I'm not sure if this IS the cause. I'm tired, time to sleep on this one.

[MasterT]

Master T. I understand your point. You mean there could be crosstalk between each gain stage via the bias feed. When I said that I used U1.2 as a buffer for the bias, it is only for feeding U1.1. While U2.1 and U2.2 where fed from the original supply. So the non-inverting and inverting bias was isolated, but the distortion remained.

You should not be using same label INPUT_BIAS if there is no connection.

 I don't see a reason of not applying 6V bias (Vcc /2)  for non-inverting first stage, as normal people always do. OPA fills better at mid-point.

 And do not overestimate "decoupling" , calculate 10uF reactance at 1 kHz and you ' d be surprised how high value is. Cap's at low freq. end are basicaly useless, all hard work do semiconductors, reference buffers etc.

[magic]

Another example of a non-linear input current (causing distortion) is for a BJT input amplifier, where the Early effect makes the base current a (not very strong) function of collector-base voltage.

Yes, this is the dominant mechanism in BJT. Another possible one is when bias cancellation is used (as in LM4562) and when those transistors get close to saturation, cancellation errors increase. LM4562 bias cancellation is known to go completely bonkers when the input stage hard-saturates (input pin less than 1V above V-), with the pin starting to sink several μA and pulling the input further towards V-.

Capacitance is more of a problem in JFETs, where it's larger. And where signal impedance can be much higher.

What is 'Input Bias'? It is the 'V Ref' output of the ADC, which is ED9821Q. It is 3V, generated by an LDO internal to the ADC.

Hmm, that's strange, 2.5V would be more typical for a 5V ADC. But it's fine if that's what this particular chip wants. LM4562 is happier too, because its output isn't rail to rail.

I'm still pondering why the distortion went down the most when I set the non-inverting stage to gain=2. This gives a bias at the output of 6v, but both inputs remain at 3v. Similarly, simply increasing the 'Input bias' to 6v also worked just as well. So I'm thinking the primary cause of distortion is to do with something other than the input nodes of the opamp. Is there any reason a non-inverting stage can't swing the output as close to the negative rail as comfortably an inverting stage?

The output stage shouldn't care much about the input common mode voltage.

Are you sure that the input didn't change? Weren't you testing with 0.5V RMS input and 1V RMS output at the gain=2 stage? Then negative peak input voltage is somewhat further from GND and input stage distortion can be lower.

In a non-inverting stage, I apply a DC bias to the non-inverting input. The signal is also applied here, so when the signal swings negative this is super-imposed on the DC bias and the op-amp input gets close to the negative rail where it can not operate well.

Exactly. With 1V RMS and 3V bias you get ~1.5V at negative peaks. This reduces Vbc of the input PNPs to practically zero and puts them on the edge of saturation. By the way, this opamp uses a topology similar to common power amplifiers, with PNP input stage and NPN current mirror with added emitter follower like in TL072.

Since the noninverting stage is AC coupled to the rest, you can simply increase its bias to 5V and this should vastly reduce distortion.

[magic]

You could also try the old NE5532 in the first stage, as it has NPN input stage which won't saturate near ground. Its tail current source will see only ~0.8V Vce, but it may not be too bad if the 2nd stage has good CMRR. Or it may be - only one way to know for sure

NE5532 also has no bias cancellation to go wrong, but it's a double-edged sword because LM4562 cancellation is similar to OP27 and attempts to correct bias variations with common mode input voltage. So when cancellation works right, it is at least conceivable that it actually reduces input current distortion.

[ssashton]

Thanks for all the replies again, it's really great to build an understanding of what was going wrong in this circuit.

Are you sure that the input didn't change? Weren't you testing with 0.5V RMS input and 1V RMS output at the gain=2 stage? Then negative peak input voltage is somewhat further from GND and input stage distortion can be lower.

Oh! You are quite right of course, I forgot about that.

I can try the NE5532, I'll see how it goes.

If I did use a 6V bias for the first non-inverting stage, are there opamps that would give particularly low CM input distortion? Better than LM4562? I see OPA1612 used a lot in high-end gear, but they are unpleasantly expensive and I hope to sell my gadget in small volume.

You should not be using same label INPUT_BIAS if there is no connection.

 I don't see a reason of not applying 6V bias (Vcc /2)  for non-inverting first stage, as normal people always do. OPA fills better at mid-point.

 And do not overestimate "decoupling" , calculate 10uF reactance at 1 kHz and you ' d be surprised how high value is. Cap's at low freq. end are basicaly useless, all hard work do semiconductors, reference buffers etc.

In my first attempt the bias was directly shared. Then, I tried to buffer the bias for the first stage because I also thought it might be a problem.

You have a good point about the decoupling capacitor ESR at audio frequencies like 1KHz. I was thinking it's about 0.5R, but I see now this is for 100KHz and 1KHz is more like 10R! I do not have much space on this circuit so I'm not sure what I can do to improve decoupling in the audio range? Also, it should be non-microphonic because the bias will directly impose the audio signal.

[MasterT]

I say reactance, not ESR.  Rc = 1  / 2* PI() *Freq. *C
IMHO picture is not quite accurate, in my experience ESR of electrolytics usually less than 0.5 OHm, and less than 10 mOhms for polymer electrolytics.
What type of C2 & C3 in your circuits?

[David Hess]

As discussed in earlier posts, the non-inverting and follower configurations suffer from various common mode sources of distortion.  There are things which can be done to improve the situation:

1. Equalize the impedance at the inverting input to match the impedance at the non-inverting input.  This will allow the common mode rejection to cancel the distortion from variation of input capacitance with common mode voltage.

2. Bootstrap the supplies to remove the variation of common mode voltage.

3. Use a discrete differential input stage.

The source of distortion with coupling capacitors is similar, a variation of capacitance with voltage.  For electrolytic capacitors, this means using a much larger value of capacitance than would strictly be required in high pass configurations.  At low impedances, this can be challenging.