PCIEXBAR Base Address for PCI Express Configuration Space

[karim]

The processor has 3 outputs: one for RAM, the second for DMI, and the third for the PCIe bus which is directly connected, for example, to a PCIe card like a graphics card. So, when the processor receives an address, it needs to know which output to use. Therefore, there must be internal registers that help it decide. For example, TOLUD contains the address range available for RAM below 4GB, and TOUUD contains the range available above 4GB. So, if I have 8GB of RAM, these two registers (TOLUD and TOUUD) would represent, for example, 7.5GB available for RAM, because 0.5GB is reserved for device addresses. The remaining 0.5GB will be allocated for MMIO addresses, starting, for example, at 0xE00000000. This is stored in the PCIEXBAR, which is directly connected to the processor. Then, the graphics card takes, for example, address 0xE0001000. Now, when the processor receives an address, it checks whether it falls within the ranges defined by TOUUD and TOLUD. If yes, it routes it to RAM. If not, it checks the PCIEXBAR; if it falls within that range, it routes it to the graphics card via the direct PCIe bus. If not, it routes it through DMI, sending it to the chipset. The chipset also has its own register defining its MMIO address range. All these registers are configured by the BIOS, and then passed to the operating system through the ACPI tables. Is what I said correct?