Page 448, middle of the paragraph about monostable multivibrators it states "the capacitor suddenly behaves as a short circuit (a capacitor likes to pass current when the voltage across it changes suddenly)". Is this correct? A short for *any* kind of current, including DC? Or just high frequency current?
Page 448, middle of the paragraph about monostable multivibrators it states "the capacitor suddenly behaves as a short circuit (a capacitor likes to pass current when the voltage across it changes suddenly)". Is this correct? A short for *any* kind of current, including DC? Or just high frequency current?
If they really mean it acts like a short, I'm surprised that the crux of their explanation is predicated upon an undisclosed (in the book, to this point) property of capacitors. And that this property isn't explained beyond the above phrase.
@ablacon64
I attach below the aforementioned table with the recommended components from the 2nd edition of the book.
Bottom of page 687 and top of 688 describes a 555's astable mode. Perhaps I'm not understanding their explanation but I think they've made an error here:
"With Qbar high, the discharge transistor is turned on, which allows the capacitor to charge toward Vcc through R1 and R2." However, a few sentences later they say "At this point, the discharge transistor turns on and shorts pin 7 to ground, discharging the capacitor through R2."
I think the first sentence may be in error as it would make more sense if the transistor were off for the capacitor to charge.
The partial paragraph below is how I think the text on pages 687 and 688 could be corrected. The strikethroughs on the Qs are meant to be overlines, I don't know how to render overlines with this forum's text editor.
"WithQhigh, the discharge transistor turns on and shorts pin 7 to ground, discharging
the capacitor through R2. When the capacitor's voltage drops below 1/3VCC, comparator 2's
output jumps to a high level, setting the flip-flop and makingQlow and the output high.
WithQlow, the transistor turns on, allowing the capacitor to start charging toward VCC
through R1 and R2. When the capacitor voltage exceeds 1/3VCC, comparator 2 goes low,
which has no effect on the SR flip-flop. However, when the capacitor voltage exceeds
2/3VCC, comparator 1 goes high, resetting the flip-flop and forcingQhigh and the output
low. At this point, the discharge transistor turns on again and shorts pin 7 to ground,
discharging the capacitor through R2. The cycle repeats over and over again. The net
result is a squarewave output pattern whose voltage level is approximately VCC - 1.5V and
whose on/off periods are determined by the C, R1, and R2."
There's still a contradiction in there. The first sentence says "With Qbar high, the discharge transistor turns on..." A couple lines below it says "With Qbar low the transistor turns on..."
My understanding is that whenever Qbar is high the transistor is on and the cap discharges. Whenever Qbar is low the transistor is off and the cap charges.
I'm glad I posted that before creating new pages!
Of course you are right, again!
Very easy to slip up even when you know what you want to say. I think the edit below may be OK:
"WithQhigh, the discharge transistor turns on and shorts pin 7 to ground, discharging
the capacitor through R2. When the capacitor's voltage drops below 1/3VCC, comparator 2's
output jumps to a high level, setting the flip-flop and makingQlow and the output high.
WithQlow, the transistor turns off, allowing the capacitor to start charging toward VCC
through R1 and R2. When the capacitor voltage exceeds 1/3VCC, comparator 2 goes low,
which has no effect on the SR flip-flop. However, when the capacitor voltage exceeds
2/3VCC, comparator 1 goes high, resetting the flip-flop and forcingQhigh and the output
low. At this point, the discharge transistor turns on again and shorts pin 7 to ground,
discharging the capacitor through R2. The cycle repeats over and over again. The net
result is a squarewave output pattern whose voltage level is approximately VCC - 1.5V and
whose on/off periods are determined by the C, R1, and R2."
At the bottom of page 772, figure 12.72 they show an SR flip-flop with NAND enable gates so a clock signal can be fed in. Why NAND? It seems like AND gates would make much more sense.
Just uploaded an updated version of the unofficial errata!
https://onedrive.live.com/redir?resid=967A90CA47FD025B!172&authkey=!ACEbpvA4f9gUlxc&ithint=file%2c.pdf
Dear TomC,
I want to say first thank you for your work. I would like to submit a candidate error for consideration. On page 18, example 1 seems to have errors in the calculations. For example, in part b, they list the voltage from point B to point C as +9 V. However, this seems to be inconsistent with the way he obtains voltage measurements for the other points (this error also extends into parts c and d). The value should be -9 V however as by how I see it, the calculation is putting the positive lead of the voltameter on B and the negative lead on C (that's how +3V was gotten for the voltage between A and C in part b as far as I can tell).
I have a question about the differential amplifier on page 446. In the top paragraph it says that a larger current will flow in the right transistor if V1 is larger than V2. Is that correct? I thought that essentially the right transistor would be cut off if V1>V2.
Thanks