Question on bypass capacitor eevblog# 859

[dilipdalton]

Dave describes the use of bypass capacitors very clearly in the EEVBLOG episode number 859.

The question I have here:
Since it is important that the capacitor be placed very close to the pin where it is needed, and multiple capacitors might be needed.
Is there a multi-capacitor device available that can do this bypass functionality?

What I mean is:
If a pin needs 3 capacitors 1uf, 100nf and 10nf to work effectively. Instead of placing 3 capacitors to do this job, can we have a single device that can do this?
In essence having a special 1.11 uf "bypass" capacitor that does the job of the 3 capacitors.

Is such a device available since this looks like a common job for the capacitor?
A simple way is - someone creating a device with the 3 capacitors (1uf, 100nf and 10nf) within it.
Maybe this device is available and called by a different name, but I am unable to find it.

The benefit of this device is that it will reduce the inductance on any additional trace length that Dave mentions from the additional capacitors that is needed.

[bob91343]

That appears to be a good idea but I have never encountered such a component.

[ataradov]

It would be a pain to manufacture, which will probably price it out of most applications except for a few space sensitive.

And in practice you don't really need that many capacitors in most cases, especially if you are limited on space.

[TimNJ]

More often than not, it seems that the multiple capacitor strategy is unwarranted and perhaps makes matters worse due to unforeseen resonant peaking in the LC tank circuit you’ve incidentally created. I’d say 2 ceramics in parallel is about the maximum you’d ever need, in practice. Dave highlighted this issue near the end of the video.

For instance, for a high speed digital type design maybe use an 0402/0603 cap (near the pin) and a 1206 slightly farther away, but no need for 0402+0603+0805+1206. Or, ditch the 1206 and use an electrolytic or polymer cap. The problem with ceramic caps is their high Q factor, and thus low ESR, which means they can accidentally start resonating pretty easily.

By the way, its the package inductance which dictates the high frequency performance of the cap, not really the capacitance so much. So, that’s why I’m using package sizes and not capacitance values.

[TimNJ]

Ah, sorry I missed your comment about trace/package inductances. Appears you didn’t need my explanation.

The issue I foresee is that the length of the package, between connections has a big influence on inductance. But if you want high capacitance, short length isn’t going to be practical. Seems like some conflicting requirements. Maybe there’s a way with clever packaging? But again, it’s the package inductance which matters most at the high frequencies, so we are probably just talking about a very wide capacitor.

The closest thing we have is probably the reverse length/width packages. For instance, 0306 instead of 0603.

[MosherIV]

I think you have miss-understood what Dave was saying.

Basically, you put local decoupling caps on each power pin of each semiconductor chip.
You may place largeish decoupling cap for sections of board where there are  large numbers of chips.
You put a large decoupling cap near the power connector of the board.

The idea is to creat tiers of local decoupling.

[David Hess]

1, 0.1, and 0.01 microfarad capacitors in parallel are not the same as 1.11 microfarads when lead inductances and resistance are taken into account.  You will sometimes see multiple decoupling capacitors of the same value in parallel for the same reason.  Parallel lead inductances lower the inductance.

Larger valued decoupling capacitors have a lower self resonant frequency so they can be further away but bulk decoupling capacitors serve an entirely different purpose; their higher ESR AC terminates the transmission line formed by the power and ground suppressing resonance.

[TimFox]

Many years ago, I gave a student technician a wiring diagram for a hand-wired Vectorboard with DIP devices.  For clarity, the power wiring was shown in the lower left-hand corner, with appropriate bypass capacitors on the power pins of each device.  He found it easier to just wire all the capacitors in parallel where the power entered the board, and showed me how clever he had been.

[eb4fbz]

No, but there are special wideband bypass capacitors with low ESR and very high SRF, so you don't need to parallel different values.

[TimFox]

Sometimes we distinguish between “reservoir” capacitors (large value, very few per board, to supply current spikes) and “bypass” capacitors (often one or more per device, to keep the devices from interfering with each other).

[Siwastaja]

If a pin needs 3 capacitors 1uf, 100nf and 10nf to work effectively. Instead of placing 3 capacitors to do this job, can we have a single device that can do this?
In essence having a special 1.11 uf "bypass" capacitor that does the job of the 3 capacitors.

Yes! Actually there is! It's the bog standard 1.11uf standard capacitor. Oh, that value does not exist, but you get the point. Use the largest value you need in the smallest package you can get.

Once you see how a capacitor consists of layers of foil, each contributing to the capacitance, you understand how ridiculous the advice of paralleling 1uF, 100nF, 10nF, 1nF, 100pF, etc. ceramics is. The only benefit it offers is that you can buy the smallest C in a smaller package, placing it closer with less stray inductance. But then again you get 1uF today in quite a small package.

This has been widely discussed here and the end result tends to be, don't go and create resonances with multiple values in parallel.

[TimFox]

An interesting problem in my past work:  a common-source JFET amplifier, with the JFET source bypassed to ground, for use at 64 MHz.  The bypass capacitor comprised 100 nF and 1 nF MLCC leaded capacitors in parallel.  To our surprise, the response from gate to drain (actually, the drain drove a transimpedance amplifier) showed a minimum at 64 MHz, but with DC power removed from the FET (open-circuiting the source bias resistor), the response showed a maximum at 64 MHz.  Separately measuring the impedance of the two capacitors in parallel showed that they did, in fact, resonate together at 64 MHz, giving the totally inappropriate response:  the 100 nF capacitor was above its SRF, and the remaining inductance resonated with the other capacitor.  (Actual capacitor values from memory.)  Of course, the signal with power removed was quite low, resulting from capacitive coupling into and out of the parallel resonant circuit to the transimpedance stage.

[David Hess]

Many years ago, I gave a student technician a wiring diagram for a hand-wired Vectorboard with DIP devices.  For clarity, the power wiring was shown in the lower left-hand corner, with appropriate bypass capacitors on the power pins of each device.  He found it easier to just wire all the capacitors in parallel where the power entered the board, and showed me how clever he had been.

I had a purchasing agent source 0.11 microfarad capacitors once as an economy measure to reduce the number of parts.

When I built a coaxial RF ground isolator for use from 2 meters to 1.2 GHz at up to 50 watts, I used 4 x 100 picofarads, 4 x 1000 picofarads, and 4 x 10,000 picofarads in parallel.  The initial version with 12 x 10,000 picofarad capacitors performed very poorly.

[Siwastaja]

Also note that due to manufacturing limitations (courtyards in PCB design), you usually only get one "very good" place for the bypass caps, and then the place for the next parallel one is considerably worse. A capacitor is much "larger" on board than it physically is.

Now, energy density of modern capacitors isn't problem; board assembly is likely a limiting factor. For example, you may decide to limit yourself to 0402 parts because you want to prototype it by hand, or use less expensive fabs. Now for say 3V3 rail, 0402 is already big enough that you can get any capacitance up to about 0.5 to 1 uF actual. The point is, you won't get any stray inductance benefits from the 1nF or 10nF parts. They are all the same, if you use the same package.

So now if you place your 10nF capacitor at the best place, all you are doing is add extra stray inductance by having to place 100nF further away. And because they both are 0402, they both add some 2nH. And that 100nF capacitor is equivalent to a stack of ten 10nF capacitors in same but thinner package, placed on top of each other. It's manufactured from multiple layers of electrodes, after all, and for your impedance plot, what matters is the distance to the closest layer.

So now the combination of 10nF and 100nF is only performing worse than if you just put the 100nF at the closest footprint. Or, if you placed two 100nF capacitors in the same footprints, instead of 10nF and 100nF. You would then be paralleling mounting inductances (to some extent; one of them is further away from the device pin, though). Additionally the risk of creating resonances is lower, and you have limited BOM lines and cost.

Ignore the advice of using many different sizes unless you know what you are doing. Similarly, ignore advice of creating split ground planes. These are tricks that are rarely useful and require careful understanding because they are full of complex traps.

Use one part# of ceramic cap on each DC bus. Adding a high-ESR bulk, though, is often a good idea, and given enough ESR, it can't do much harm, and can potentially do good for damping. This is less risky even if you don't analyze it well.

[T3sl4co1l]

Relevant discussion: https://www.eevblog.com/forum/projects/location-and-value-of-decoupling-capacitors-(not-bga)/

Dave misses the parallel resonance between capacitors, which can make things actively worse than just one capacitor.

It seems to be an example of an idea that catches on, that is believable, but just difficult enough to verify (i.e. you have to know these things already, or build a representative simulation, or measure it with a VNA and who has one of those?) that it's accepted at face value rather than analyzed.  A meme.

Tim