Signal naming styles in schematics

[Benta]

This post is the result of a discussion in a different thread concerned with how to draw nice schematics. It relates mainly to digital design.
It has quite a lot to do with semantics on signal/net naming.

To me, a schematic is made to explain the function of a circuit, and creating an IC symbol that's the same as the pin layout makes little sense. Signal grouping is the way to go on a symbol.

Pin names are already defined in the supplier datasheets, and it's a good idea to stick with those on the parts.

But there are lots of nets that need their own name, simply because they connect parts with different signal names is a net, and you'll need a name that brings all that together.

Here's my style, intended as an invitation for discussion:

1: Always create a name that indicates the net's function. RESET, ENABLE, CLK, DISABLE, LOAD, CLK_INHIBIT etc. are good basic names. They describe the action of the net when the signal is asserted.
2: Indicate the assertion level. This I do by using this style: RESET(L), ENABLE(H), LOAD(L) etc. This indicates the assertion level without compromising the net's functional name.
Silicon suppliers tend to use either a "/" before a name (/RESET) or a bar above the name. I don't like this, as it mixes up assertion with signal level.

Examples of bad names are NRESET, NOT_RESET, NO_CLK etc.
Why? Because they describe what a net does NOT do. So how do I know what it DOES do?

This convention is not invented by me, but was taught in university based on this brilliant gentleman's book:

https://www.amazon.com/Engineering-Approach-Digital-Design/dp/B001947XOC

[langwadt]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

[S. Petrukhin]

You have good ideas, but they are not yet known to many people.

I'll easily understand /Reset or nRESET or Reset with a dash at the top, but I won't understand Reset (L).
What does (L) mean? I might think it's a Reset for a block named L. It doesn't seem logical to me.

And personally, I don't see anything wrong with simultaneously specifying the name of the signal and its present position.

Do you have any arguments other than German pedantry and attention to detail?
I can't buy the mentioned book and I don't know what am arguments.

[Benta]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

What standard? Reference, please. And () are not special characters.

[Benta]

And personally, I don't see anything wrong with simultaneously specifying the name of the signal and its present position.
Do you have any arguments other than German pedantry and attention to detail?

To your last question: that my locale is Germany does not mean I'm German. Don't jump to conclusions.

Second: yes, there are good reasons for separating assertion (which is the function of the net) and assertion level (which is the logic voltage level of the signal).

Suppose your RESET signal passes through an inverter. Then it suddenly needs to be called NRESET. and after another inverter, it's RESET again.

RESET(H), RESET(L), RESET(H) solves this and makes the schematic much easier to read and analyse.

This concept of separating function and actual logic level is not only known from Fletcher, by the way.

[langwadt]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

What standard? Reference, please. And () are not special characters.

the ginormous amount of schematics and datasheets since the dawn of time that uses it. 

sure () is not "special" but they might have special meaning in other tools down the line

[langwadt]

And personally, I don't see anything wrong with simultaneously specifying the name of the signal and its present position.
Do you have any arguments other than German pedantry and attention to detail?

To your last question: that my locale is Germany does not mean I'm German. Don't jump to conclusions.

Second: yes, there are good reasons for separating assertion (which is the function of the net) and assertion level (which is the logic voltage level of the signal).

Suppose your RESET signal passes through an inverter. Then it suddenly needs to be called NRESET. and after another inverter, it's RESET again.

RESET(H), RESET(L), RESET(H) solves this and makes the schematic much easier to read and analyse.

This concept of separating function and actual logic level is not only known from Fletcher, by the way.

what difference does it make if NRESET changes to RESET, vs. RESET(L) changes to RESET(H) ?

[S. Petrukhin]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

What standard? Reference, please. And () are not special characters.

Same as uF. 
Someone once used out of desperation and liked by almost everyone, which quickly came into use.
Clear without explanation, logical, convenient, but, of course, not yet issued by officials in the form of a large and muddy paper. 

And programmers write !Reset, or ~Reset, or not Reset, or not(Reset).

It became normal.  You understood nRESET, and I wouldn't understand reset (L). Spare my feelings. 

[JohnnyMalaria]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

What standard? Reference, please. And () are not special characters.

"Standard" has a number of meanings, including something established by authority, custom, or general consent as a model or example. Prefixing a signal with N to indicate that the line needs to be pulled low has been done for decades. My first exposure to it was for a Z80. i.e., it is customary and, therefore, standard.

EDIT: Although the official Zilog documentation uses the "line-above-the-name" convention which, when you glance at the pinout diagram, very quickly reveals those signals that need to be pulled low. It also avoids the confusion with signals starting with N before modifying with an N-prefix. e.g, NMI.

[S. Petrukhin]

And personally, I don't see anything wrong with simultaneously specifying the name of the signal and its present position.
Do you have any arguments other than German pedantry and attention to detail?

To your last question: that my locale is Germany does not mean I'm German. Don't jump to conclusions.

Second: yes, there are good reasons for separating assertion (which is the function of the net) and assertion level (which is the logic voltage level of the signal).

Suppose your RESET signal passes through an inverter. Then it suddenly needs to be called NRESET. and after another inverter, it's RESET again.

RESET(H), RESET(L), RESET(H) solves this and makes the schematic much easier to read and analyse.

This concept of separating function and actual logic level is not only known from Fletcher, by the way.

German pedantry is a compliment. Being in German culture, you are probably exposed to it. this is a positive print. 

I understand your idea not to change the name of the signal in whatever position it is. This is a perfectly understandable and good idea. But that is why they do not write NRESET, but write nReset/nRESET - the prefix is clearly shown. It is compact and does not risk suffering from gaps.

By the way, I remembered: even saw schemes with a similar designation under discussion. I didn't understand the letters in parentheses at the time, honestly. 

[AlfBaz]

Pin names are already defined in the supplier datasheets, and it's a good idea to stick with those on the parts.

Some manufacturers name the pins based on the port number and then give a table listing alternate functions while others will name the pin with every function it can do.
What I've settled on is creating the original symbol with port name only such as PA0 PA1 etc. When placed on the schematic I name the net based on the alternate pin function used in that design

2: Indicate the assertion level. This I do by using this style: RESET(L), ENABLE(H), LOAD(L) etc. This indicates the assertion level without compromising the net's functional name.
Silicon suppliers tend to use either a "/" before a name (/RESET) or a bar above the name. I don't like this, as it mixes up assertion with signal level.

Examples of bad names are NRESET, NOT_RESET, NO_CLK etc.
Why? Because they describe what a net does NOT do. So how do I know what it DOES do?

Active High and Active Low signals are one of the first things taught in digital electronics. It's well established in most text books and in most schematics that an undecorated name is active high and one decorated with N, / or overbar is active low.
The examples of bad names you gave tell ME exactly what they do AND how they do it

[JohnnyMalaria]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

What standard? Reference, please. And () are not special characters.

Well, good luck when you start to write any software to control your hardware and you want to use variable names the same as the signal names. Which would cause problems: NRESET or RESET(L)?

[SVFeingold]

Silicon suppliers tend to use either a "/" before a name (/RESET) or a bar above the name. I don't like this, as it mixes up assertion with signal level.

Not sure I understand this part. I personally do the bar above the name. Its explicit purpose is to define the signal level, no? ENABLE with a bar means "enable when low." Without a bar means "enable when high." Seems perfectly straightforward to me. Am I misunderstanding something?

[ledtester]

I suppose you could try to satisfy everybody...

$$
\text{/n}\overline{\text{RESET}}\text{(L)}
$$

[langwadt]

I suppose you could try to satisfy everybody...

$$
\text{/n}\overline{\text{RESET}}\text{(L)}
$$

some put the n at the end

[S. Petrukhin]

Silicon suppliers tend to use either a "/" before a name (/RESET) or a bar above the name. I don't like this, as it mixes up assertion with signal level.

Not sure I understand this part. I personally do the bar above the name. Its explicit purpose is to define the signal level, no? ENABLE with a bar means "enable when low." Without a bar means "enable when high." Seems perfectly straightforward to me. Am I misunderstanding something?

The bar above the name is difficult to reproduce in the description text - ordinary text editors have no desire to help you with this. And when programming, if it's a digital circuit, you'll have a hard time specifying variable names that match the pin names.

[S. Petrukhin]

I suppose you could try to satisfy everybody...

$$
\text{/n}\overline{\text{RESET}}\text{(L)}
$$

[tooki]

I suppose you could try to satisfy everybody...

$$
\text{/n}\overline{\text{RESET}}\text{(L)}
$$

FTFY:$$
\text{!/n}\overline{\text{RESET}}\text{(L)}
$$

[tooki]

Silicon suppliers tend to use either a "/" before a name (/RESET) or a bar above the name. I don't like this, as it mixes up assertion with signal level.

How do you figure? It's telling you that it's active low. What do you even mean by "signal level"??

[nigelwright7557]

NRESET, etc. is standard, doesn't use special characters and conveys exactly the same information as RESET(L), ENABLE(H), LOAD(L)

On PIC's I use /MCLR VCC AND VDD
These are as datasheet as pin names.

[S. Petrukhin]

I suppose you could try to satisfy everybody...

$$
\text{/n}\overline{\text{RESET}}\text{(L)}
$$

FTFY:$$
\text{!/n}\overline{\text{RESET}}\text{(L)}
$$

$$
\text{~!/n}\overline{\text{ReseT}}\text{n\!~(L)}
$$

[tggzzz]

This convention is not invented by me, but was taught in university based on this brilliant gentleman's book:

https://www.amazon.com/Engineering-Approach-Digital-Design/dp/B001947XOC

Fletcher's book is indeed excellent.

Consider a TTL IC where an input has to be held at 0V in order to reset the IC. That could be represented by either of:

• the name "RESET" inside the IC outline, with a negating "O" outside the IC outline
• the name "NRESET" or similar inside the IC outline, without a negating "O" outside the IC outline

Personally I prefer the former.

That technique can also be used when using the deMorgan equivalents of NAND, NOR, AND, OR gates, in order to visually "remove" the active low etc.

Of course, active low inputs are predominately an artifact of TTL logic which ahd asymmetrical logic levels and strengths, where pull-down was stronger than pull-up. Moder CMOS logic is symmetrical, so the benefit of having an active low input is moot.

[S. Petrukhin]

This convention is not invented by me, but was taught in university based on this brilliant gentleman's book:

https://www.amazon.com/Engineering-Approach-Digital-Design/dp/B001947XOC

Fletcher's book is indeed excellent.

Consider a TTL IC where an input has to be held at 0V in order to reset the IC. That could be represented by either of:

• the name "RESET" inside the IC outline, with a negating "O" outside the IC outline
• the name "NRESET" or similar inside the IC outline, without a negating "O" outside the IC outline

Personally I prefer the former.

That technique can also be used when using the deMorgan equivalents of NAND, NOR, AND, OR gates, in order to visually "remove" the active low etc.

Of course, active low inputs are predominately an artifact of TTL logic which ahd asymmetrical logic levels and strengths, where pull-down was stronger than pull-up. Moder CMOS logic is symmetrical, so the benefit of having an active low input is moot.

Yes, in TTL the flying input has state 1, in CMOS it is an undefined state. But the negation of the RESET signal, as I think, has a different origin, logical. This is also used in industrial automation: all readiness signals and emergency sensors must explicitly give a value of 1 in the normal state, and in the event of an accident, give 0.

[langwadt]

This convention is not invented by me, but was taught in university based on this brilliant gentleman's book:

https://www.amazon.com/Engineering-Approach-Digital-Design/dp/B001947XOC

Fletcher's book is indeed excellent.

Consider a TTL IC where an input has to be held at 0V in order to reset the IC. That could be represented by either of:

• the name "RESET" inside the IC outline, with a negating "O" outside the IC outline
• the name "NRESET" or similar inside the IC outline, without a negating "O" outside the IC outline

Personally I prefer the former.

That technique can also be used when using the deMorgan equivalents of NAND, NOR, AND, OR gates, in order to visually "remove" the active low etc.

Of course, active low inputs are predominately an artifact of TTL logic which ahd asymmetrical logic levels and strengths, where pull-down was stronger than pull-up. Moder CMOS logic is symmetrical, so the benefit of having an active low input is moot.

Yes, in TTL the flying input has state 1, in CMOS it is an undefined state. But the negation of the RESET signal, as I think, has a different origin, logical. This is also used in industrial automation: all readiness signals and emergency sensors must explicitly give a value of 1 in the normal state, and in the event of an accident, give 0.

for reset it also makes sense to have things held in reset during powerup

[dmills]

Personally for me, nReset and Reset are DIFFERENT nets (possibly with an inverter between them, possibly being driven by two pins on an FPGA to save on the external inverter, whatever), and as such absolutely must have different names.

nReset, Reset_n, /Reset, I know what they all mean and there is useful information in that negation when I am poking around someone else's design or doing review.

The bigger question is what do we do about different logic levels? I like MOSI_1V8 and MOSI_3V3 for example, but other opinions would be appreciated.

Speaking of SPI, this is one place where I often do NOT follow the datasheet pin naming, SDO for example, is depending on which device, either MISO or MOSI, (Or whatever the yanks will tell me I should be using to avoid giving offence) naming that net SDO is just asking for trouble.
Note that sometimes the CAD tools impose requirements, Altium for example likes _P,_N on the end of differential pairs and will bitch if not present.

Net names should give clarity to designs, anything that does not make the ting easier to follow is to be avoided.
That style of schematic with the little stubs of net names and no actual connectivity drawn has to die, it is impossible to follow.

[tggzzz]

The bigger question is what do we do about different logic levels? I like MOSI_1V8 and MOSI_3V3 for example, but other opinions would be appreciated.

That sounds like you are confusing analogue voltages with digital signals.

[dmills]

You are very lucky these days if your digital signals are all one logic level for high.

My current design has 1.5V (40R terminated, DDR3 Data and address), 1.5V differential (DDR Clocks), 80 ohm terminated, USB (90 ohm lines), LVDS (100R diff pairs), 1.8V LVCMOS, 2.5V LVCMOS, 3.3V LVCMOS, some 5V doings, some 12Gb/s CML down at the 1V common mode and a few hundred mV signal level, and that is before we get to the nominally 'analogue' doings (All the fast stuff is functionally analogue, if you have to look at eye diagrams then it is analogue design).

FPGA Projects be like that.

The days when all logic had the same reference voltage are LONG GONE, that basically never happens to me on work projects these days and annotating nets with expected voltage is valuable at review time for making checking easier.

[richard.cs]

No mention of directionality yet? At work we've started naming UART signals with things like "uC_TX_ext_RX", "uC_RX_ext_TX", "Modem_TX_Controller_RX" because too many instances of TX/RX crossovers escaped review, and many of the micros we use don't allow us to fix it by switching around in software. It seems to have helped, fewer screwups since.

[dmills]

RS232 is a hot mess for that, the whole DCE/DTE thing.
But that is why in my view SDO and SDI are right out and MOSI and MISO in for SPI, been bitten by a contractor.

Regards, Dan.

[richard.cs]

But that is why in my view SDO and SDI are right out and MOSI and MISO in for SPI, been bitten by a contractor.

Yes, I think it was that SPI naming convention that inspired the UART one.

[tggzzz]

You are very lucky these days if your digital signals are all one logic level for high.

My current design has 1.5V (40R terminated, DDR3 Data and address), 1.5V differential (DDR Clocks), 80 ohm terminated, USB (90 ohm lines), LVDS (100R diff pairs), 1.8V LVCMOS, 2.5V LVCMOS, 3.3V LVCMOS, some 5V doings, some 12Gb/s CML down at the 1V common mode and a few hundred mV signal level, and that is before we get to the nominally 'analogue' doings (All the fast stuff is functionally analogue, if you have to look at eye diagrams then it is analogue design).

FPGA Projects be like that.

The days when all logic had the same reference voltage are LONG GONE, that basically never happens to me on work projects these days and annotating nets with expected voltage is valuable at review time for making checking easier.

I understand where you are coming from, but if you go in that direction where do you stop? 50ohm, differential, terminations...

Presuming the tool allows it, I would prefer to set a net's attribute to indicate voltage. That might enable further automated DRC.

Failing that, I'd stick a comment on the schematic.

[madires]

2: Indicate the assertion level. This I do by using this style: RESET(L), ENABLE(H), LOAD(L) etc. This indicates the assertion level without compromising the net's functional name.

Don't forget to add a legend explaining that naming convention to prevent any confusion.

[dmills]

I understand where you are coming from, but if you go in that direction where do you stop? 50ohm, differential, terminations...
Presuming the tool allows it, I would prefer to set a net's attribute to indicate voltage. That might enable further automated DRC.

Failing that, I'd stick a comment on the schematic.

My usual practise is that everything gets a net class that deals with the impedance and such, and that I don't designate voltage on things like LVDS or DDR3 when it ought to be clear from the context.

Things like SPI, I2C, and other random LVCMOS stuff however do get the voltage tacked on, especially if a port name heading off to another page or such where notes on the originating page may not be remembered.

There is little point in getting dogmatic about any of this stuff, you can wind up so far down the 'coding standard' rabbit hole that you stop asking the two questions that really matter : Does it make the intent clearer for the next guy (Or me in a year), and does it help the reviewers to spot errors? Consistency is nice, but those two questions are the IMPORTANT ones. 

Regards, Dan.

[tggzzz]

There is little point in getting dogmatic about any of this stuff, you can wind up so far down the 'coding standard' rabbit hole that you stop asking the two questions that really matter : Does it make the intent clearer for the next guy (Or me in a year), and does it help the reviewers to spot errors? Consistency is nice, but those two questions are the IMPORTANT ones. 

Very true

To a large extent it is a matter of taste, and what is tasteful here isn't necessarily tasteful there.

"A foolish consistency is the hobgoblin of a little mind" - Ralph Waldo Emerson.

[emece67]

.

[nigelwright7557]

The biggest danger of using net names is accidentally duplicating one.
I try to draw gates fairly close so I just run the nets without a name.
This changes with things like GND and VCC when I just use net name tags.