Understanding address decoders of a RAM IC

[gkmaia]

I am trying to understand how the decoders of this 256k RAM would look like.

As I have 16 address inputs, that made me think about on 8x256 decoder for rows and another 8x256 decoder for columns. But that would only give me 65,536 registers.

So to achieve 262,144 registers with 16 address inputs, how the decoders should look like?

[jmelson]

I count 18 address bits.  That's 256 K words of 8 bits each.

Jon

[Nerull]

0-17 isn't 16 inputs...

[gkmaia]

That is right. I did count it wrong.

In a case of 18 lines how does the decoders would be configured?

[Berni]

Well its just a decoder.

18 signals go in in and 262144 signals come out. Depending on what address is passed in the decoder selects the appropriate output and signals the appropriate memory row to be selected.

Tho in the actual chip design its probably not one big decoder for practical reasons. You would likely have the memory array split up into many parts (could be only 4 could be over 1024). Then you could have a decoder with only as many output as there are memory sections, this would then activate that section where a separate smaller address decoder would find the right byte in that section. Because the sections of memory are now smaller means that the decoder in each section can also be smaller. But this is just an implementation detail, functions just the same as one big decoder so the datasheet will show it like that for simplicity.