Using a CPLD to consolidate 74HC-series logic

[David00]

Have an old proprietary 8088-based computer. Would like to create some specially addressed IO registers. Know how to do this using 74HC components; I’d need 6 basic gate packages (HC00, etc.) to create address decoders, and 8 standard 74HC devices (3x HC373, 2x HC688, 1x HC74 and 2x HC00). So 14 DIP packages in total. This is all fine - but it would be great to reduce the package count.

There are around 22 inputs (AD0..7, A8..15, ALE, IOM, XXX, RD, WR, EACK) and 8 outputs (AD0..7). So wondering if this could be implemented in a CPLD, a technology I know very little about in practice. It seems there are few 5 V CPLDs available these days, and many modern CPLDs have a large number of pins that would be unused.

Know I could get a 3.3 V or less CPLD and use level shifters - but aiming for a single chip solution to make it worth while. Also need a package that I can hand solder, with an optimum number of pins, e.g. don’t want a 144 pin device. In my world a DIP or SOIC is still best, am OK with surface mount like 32-pin QFP but BGA (or anything socketed) wouldn't work. Being able to specify which pin is which signal would be useful. Prefer a cheap or better still free CPLD programming system.

Not interested in implementing the 8088-based computer in an FPGA; that would be missing the point.

So, CPLD criteria ranked below:

•   Package type – must be easy to hand solder (must have)
•   Supports 5 V directly (must have)
•   Optimum number of pins (would like to have)
•   Configurable pins  (nice to have)
•   Cost

Have seen a few similar posts about using CPLDs to implement 74-series devices, but they didn’t address my specific case. Am happy to use obsolete parts, and expect this is probably the only way to meet the 5 V criterion.

Is there a reasonably easy way to do this? Am hoping someone who has experience of older CPLDs can suggest an approach.

David00

[David Hess]

It is absolutely possible.  One of the big applications for PLDs was address decoding.

[David00]

@David Hess - are you able to elaborate pls? I know PLDs were/are used for address decoding. I'm asking about a specific scenario with constraints.

[RomDump]

Have seen a few similar posts about using CPLDs to implement 74-series devices, but they didn’t address my specific case. Am happy to use obsolete parts, and expect this is probably the only way to meet the 5 V criterion.

Is there a reasonably easy way to do this? Am hoping someone who has experience of older CPLDs can suggest an approach.

David00

Please google Microchip ATF1508AS. Should meet your needs.

[mikeselectricstuff]

Couple of ATF22V10s - need 2 due to number of inputs

[Ian.M]

Microchip still have a number of ex-Atmel 5V CPLDs in current production.  See https://www.microchip.com/ParamChartSearch/chart.aspx?branchID=30024 and select the two voltage ranges that include 5V.  There's even a few DIP package devices including some that can replace 16V8 and 22V10 PALs.  They also have the software required - see https://www.microchip.com/design-centers/fpgas-and-plds/splds-cplds/pld-design-resources

The official programming cable (for the ATF15xx devices) is  £46 (+VAT): https://www.microchipdirect.com/product/ATDH1150USB
or if you are lucky, you may already have a universal programmer that supports them, not just *claims* to support them!

[dferyance]

I've not used them but you should check out GreenPAK. It fits much of what you are looking for regarding consolidating chips and supporting 5V. They target very small SMD as the point is to save power, cost and space, but they do have DIP breakouts for development tools. Most of their chips are OTP but there are a few that you can reprogram. Their basic dev board is $25 so not too bad to try out.

I have used ATF22V10 in vintage work. The nice thing too is it stays truer to the vintage date than something modern. The pins aren't as programmable as CPLDs but it is a much simpler device. wincupl is a pain to run on modern systems though, I had to run it in an old VM.

[David00]

@RomDump - Isn't the ATF1508AS a 100 pin device? That's too many pins...

[David00]

@mikeselectricstuff - thanks  , I had been looking at an ATF750 but couldn't find a sub-$300 programmer for it. So was looking at the ATF22V10, which my old VP-280 can program. Your post has encouraged me to look even closer...

[David00]

@dferyance - thanks, you're the second person to mention the ATF22V10 which looks promising...

[NivagSwerdna]

It seems there are few 5 V CPLDs available these days

Just recently I used a GAL16V8 (easily programmed with a cheapo TL866 programmer) and there are a few more devices out there with more pins.... ATF22V10?
You need to be able to express your equations in a tool such as "Logic Friday" and make sure they make sense and then express in a HDL of some kind... I used ABEL... and then program.
It's quite fun! (especially if you missed out on CPLDs the first time around!)

[David00]

@Ian.M - Many thanks, that's helped a lot 

[David00]

NivagSwerdna - Thanks. I have/use Logic Friday. I don't feel I've missed out...

[Ian.M]

I should point out that the older Atmel CPLDs that are usable as pinout compatible PAL replacements, used hardware programming tools that are no longer available from Microchip so 3rd party tools are the only option.

[mikeselectricstuff]

It seems there are few 5 V CPLDs available these days

Just recently I used a GAL16V8 (easily programmed with a cheapo TL866 programmer) and there are a few more devices out there with more pins.... ATF22V10?
You need to be able to express your equations in a tool such as "Logic Friday" and make sure they make sense and then express in a HDL of some kind... I used ABEL... and then program.
It's quite fun! (especially if you missed out on CPLDs the first time around!)

If CUPL (WinCUPL) is still available I'd reccommend that - for stuff like address decoding it's pretty straightforward and you can probably find some examples to get you started. Here's an example that looks close to what you are doing :

Code: [Select]

Device          G20V8ALCC;

/************************************************************************/
/* This device generates the chip select signals for the I/O functions. */
/* It also enables the data bus transceiver for both memory and I/O     */
/* write cycles.                                                        */
/************************************************************************/

/** Inputs **/

pin [2..7,9,10] = [a9..2] ;             /* system addresses a2 - a9     */
pin 11     = !memw ;                    /* memory write strobe          */
pin 12     = !iow ;                     /* i/o write strobe             */
pin 13     = !ioacc_in ;                /* same signal as ioacc         */
pin 16     = !memacc ;                  /* on-board memory access       */

/** Outputs **/

pin 18     = !ioacc ;                   /* on-board I/O being accessed  */
pin 19     = !parport ;                 /* parallel port chip select    */
pin 20     = !rtclk ;                   /* real-time clock chip select  */
pin 21     = !serport2 ;                /* serial port #2 chip select   */
pin 23     = !serport1 ;                /* serial port #1 chip select   */
pin 24     = !wrbuff ;                  /* xceiver enable - write cycle */

/** Declarations and Intermediate Variable Definitions  **/

field   ioaddr    = [a9..2] ;
serport1_eqn      = ioaddr:[2F8..2FF] ;  /*******************************/
serport2_eqn      = ioaddr:[3F8..3FF] ;  /*          I/O Address        */
rtclk_eqn         = ioaddr:[100..11F] ;  /*             Ranges          */
parport_eqn       = ioaddr:[1F4..1F7] ;  /*******************************/

/** Logic Equations **/

wrbuff            = memacc & memw # ioacc_in & iow ;
ioacc             = serport1_eqn # serport2_eqn # rtclk_eqn #
                    parport_eqn ;
serport1          = serport1_eqn ;
serport2          = serport2_eqn ;
rtclk             = rtclk_eqn ;
parport           = parport_eqn ;


[David00]

Couple of questions:

1.   I need 22 inputs and 8 outputs. But those 8 outputs are for AD0..7 (8088 multiplexed Address/Data lines), which are also 8 of my inputs. If I use a single ATF22V10 which has 12 input pins and 10 I/O pins, I can allocate 8 of those I/O pins to AD0..7 for input and output, and use the remaining 2 as inputs, along with the other 12 inputs. Correct?

2.   I’ve downloaded WinCUPL and can see how to configure an address decoder. But for the more complex 74HC parts I want to integrate, such as the  HC373, how can I represent this within WinCUPL? Have started to look through the user manual, I need to use statements like .L for a latch input, correct? Can anyone tell me all of the commands to describe an 8-bit latch?

[pwlps]

Couple of questions:

1.   I need 22 inputs and 8 outputs. But those 8 outputs are for AD0..7 (8088 multiplexed Address/Data lines), which are also 8 of my inputs. If I use a single ATF22V10 which has 12 input pins and 10 I/O pins, I can allocate 8 of those I/O pins to AD0..7 for input and output, and use the remaining 2 as inputs, along with the other 12 inputs. Correct?

2.   I’ve downloaded WinCUPL and can see how to configure an address decoder. But for the more complex 74HC parts I want to integrate, such as the  HC373, how can I represent this within WinCUPL? Have started to look through the user manual, I need to use statements like .L for a latch input, correct? Can anyone tell me all of the commands to describe an 8-bit latch?

You might find this discussion useful:
https://groups.google.com/g/sci.electronics.design/c/bxlmLQjGijM?pli=1

NB. I used 22V10s (20 years ago ?), programmed them in ABEL and it was a lot of fun. I don't have any experience with WinCUPL programming but I remember at that time I found the PLD-style programming tools rather awkward compared to ABEL.

[mikeselectricstuff]

Couple of questions:

1.   I need 22 inputs and 8 outputs. But those 8 outputs are for AD0..7 (8088 multiplexed Address/Data lines), which are also 8 of my inputs. If I use a single ATF22V10 which has 12 input pins and 10 I/O pins, I can allocate 8 of those I/O pins to AD0..7 for input and output, and use the remaining 2 as inputs, along with the other 12 inputs. Correct?

from memory, yes, but there are a few constraints that my memory is too hazy to remember - maybe that output enables and clocks on latches are global with a fixed pin, but I may be thinking of a different device

2.   I’ve downloaded WinCUPL and can see how to configure an address decoder. But for the more complex 74HC parts I want to integrate, such as the  HC373, how can I represent this within WinCUPL? Have started to look through the user manual, I need to use statements like .L for a latch input, correct? Can anyone tell me all of the commands to describe an 8-bit latch?

CUPL comes with lots of examples, have a browse through them, particularly those for 22V10 and 16V8 devices. and you will probably find most of what you need.
e.g. this barrel shifter example shows how latch inputs work :

Code: [Select]

Name      Barrel22;
Partno    CA0006;
Date      05/11/89;
Revision  02;
Designer  Kahl;
Company   Logical Devices, Inc.;
Assembly  None;
Location  None;
Device    g22V10;

/****************************************************************/
/*                                                              */
/* 8-Bit Registered Barrel Shifter                              */
/*                                                              */
/* This 8-bit registered barrel shifter takes 8 data inputs     */
/* and cyclically rotates the data from 0 to 7 places under     */
/* control of the select ( S0, S1, S2 ) inputs.  A SET input    */
/* can be used to initialize the outputs to the all ones state  */
/****************************************************************/
/* Allowable Target Device Types :  PAL22V10                    */
/****************************************************************/

/**  Inputs  **/

PIN 1           = clock;        /* Register Clock               */
PIN [2..9]      = [D7..0];      /* Data Inputs                  */
PIN [10,11,14]  = [S2..0];      /* Shift Count Select Inputs    */
PIN 13          = !out_enable;  /* Register Output Enable       */
PIN 23          = preset;       /* Set to Ones Input            */

/**  Outputs  **/

PIN [15..22] = [Q7..0];         /* Register Outputs             */

/** Declarations and Intermediate Variable Definitions **/

field shift  = [S2..0];         /* Shift Width Field            */
field input  = [D7..0];         /* Inputs Field                 */
field output = [Q7..0];         /* Outputs Field                */

/** Logic Equations **/

output.d  =  [D7, D6, D5, D4, D3, D2, D1, D0]  &  shift:0
          #  [D0, D7, D6, D5, D4, D3, D2, D1]  &  shift:1
          #  [D1, D0, D7, D6, D5, D4, D3, D2]  &  shift:2
          #  [D2, D1, D0, D7, D6, D5, D4, D3]  &  shift:3
          #  [D3, D2, D1, D0, D7, D6, D5, D4]  &  shift:4
          #  [D4, D3, D2, D1, D0, D7, D6, D5]  &  shift:5
          #  [D5, D4, D3, D2, D1, D0, D7, D6]  &  shift:6
          #  [D6, D5, D4, D3, D2, D1, D0, D7]  &  shift:7;

output.sp = preset;             /* synchronous preset           */

output.oe = out_enable;         /* tri-state control            */

output.ar = 'h'00;              /* asynchronous reset not used  */


[ebclr]

https://www.xilinx.com/support/documentation/user_guides/ug445.pdf

[BrianHG]

Anything on this page should work:
5v PLDs with 40-84 pins

There is even a 40pin dip version, except, you pay for the plastic and get 24 IOs instead of 32 or more.  Some have 32 logic cells while others have 64, or 128 for the larger ones.  Though, bread-boarding testing may make the 7$ version good for testing until you build a PCB to hold the J-lead 44/84 pin versions.

[Ian.M]

You are referring to the ATF2500C-20PU.   Excluding Vcc and Gnd, the other 14 pins are inputs, and the O.P's design needs 22 inputs, so only having 32 I/O pins in a 40 pin package shouldn't be a significant limitation.  Its got just enough inputs and I/Os to implement two 8 bit ports on the O.P's bus so one port with whatever control lines are required shouldn't be a problem.

[BrianHG]

You are referring to the ATF2500C-20PU.   Excluding Vcc and Gnd, the other 14 pins are inputs, and the O.P's design needs 22 inputs, so only having 32 I/O pins in a 40 pin package shouldn't be a significant limitation.  Its got just enough inputs and I/Os to implement two 8 bit ports on the O.P's bus so one port with whatever control lines are required shouldn't be a problem.

24IOs, + 13 dedicated inputs + 1 clock, not 32 IO.  However, since address lines can go to the dedicated inputs, this is fine.  It's that ugly 7.86$ VS the 1.93$ PLCC versions.  Though, there do exist 44LCC sockets which have through-hole pins on the bottom.

Example: https://www.digikey.com/en/products/detail/assmann-wsw-components/A-CCS-044-Z-T/821811

It still costs much less to buy the LCC PLD and the IC socket with through-hole mounting.  Not to mention the LCC version of the PLD has 32IOs instead or 24IOs, both with additional dedicated input pins only. (Extra IOs allow for an additional decoded bidir 8bit port with a CLK pulse/data ready output, or direction signal.)

[Ian.M]

Thank you for correcting my I/O pin count FUBAR.   Its probably not a sufficient cost saving to make it worth messing with PLCC in a one-off or very low volume DIP through-hole project, but using TQFP-44 package CPLDs on off-the-shelf TQFP to DIL breakout boards would certainly be an option.  The TQFP-44 ATF1502A looks interesting with 64 macrocells and speed grades down to 7ns.

[BrianHG]

Thank you for correcting my I/O pin count FUBAR.   Its probably not a sufficient cost saving to make it worth messing with PLCC in a one-off or very low volume DIP through-hole project, but using TQFP-44 package CPLDs on off-the-shelf TQFP to DIL breakout boards would certainly be an option.  The TQFP-44 ATF1502A looks interesting with 64 macrocells and speed grades down to 7ns.

-> ATF1504AS-7JX44 <- This is the 64 macrocell version.  At 5.71$, you are at the price of the smallest MAX10 FPGA with built in bootprom, though, 3.3v or less voltage on the IOs, or a small Lattice MachX02.  Tolerable.

[Ian.M]

You continue to pick up on my FUBARs at an alarming rate.  Its a good thing I'm not ordering parts for a project at the moment isn't it!   

Its just random curiosity, but are there any 3.3V FPGAs still on the market with 5V tolerant I/Os (i.e. suitable for direct interfacing to 5V logic with TTL thresholds) and affordable development tools (i.e affordable enough for a hobbyist one-off  project) that you could recommend?