Ah yes. They are parallel in your schematics. That is not wrong. The Net connections are correct. But while doing the layout, you need to pay attention to connect one 100nF to pin 1, one to pin 24, one to pin 36 and one to pin 48. So that, there are 4 VDD connections and 4 100nF capacitors. You will route 3.3V to the capacitor then to the pin for each of them. Each pin will draw the current from its related 100nF capacitor. Those capacitors will draw from 10uF capacitor and goes like that.
If you don't use 120ohm ferrite, then you still need to connect that 1uF and 10nF to pin 9.