who uses fpga's

[Capernicus]

What I need to do now is get some free simulation software,  work out how much estate I need, and get the cheapest FPGA that'll fit the hardware description.

I was looking at buying a rack of smaller ones or 1 big one,  but 1 big one was cheaper.

SPARTAN 6 XC6SLX9  has ~10,000 CLBS - and its worth $40  - a 16'r rack would be  146,432 CLBS cost $640 (but less if u get bulk)
SPARTAN 6 XC6SLX150T has 147,443 CLBS (so its only 1k more) - and it costs  ~$340....   so its actually cheaper just to buy 1 big one in this case.

My idea is really simple.
I don't need the video signals,  I just need the game model to play through with random controls, then the score goes into a max circuit, the one that scored the highest out of the whole lot of testing every 100 milliseconds is what the computer does, to do the Ai.  It helps if its an FPGA because u get the "game samples" at the HZ of the machine just with the electrical delay slowing it down. (so its bloody quick!)

[james_s]

That seems like an awfully strange way of generating random numbers. In most cases the score is going to be zero if you try to play a game like Pong with random controls, save for the occasional fluke where the ball hits a paddle once or twice. You could probably fit several thousand instances of a game like that in a XC6SLX9 though, that's quite a large FPGA by my standards. Just for reference, I did a few classic games like Super Breakout, Sprint 2 and others of the same generation and they consume about half the resources of the EP2C5T144C8 I used, quite a small FPGA by modern standards. The speed only matters for the video signal, you can easily clock the system many times faster than the original except that makes the video timing all wrong. Using a CRO as a vector monitor I can run Asteroids at something like 20x speed even on an old FPGA, it's completely unplayable at that point.

The software for any of the major FPGA players is available free for personal use. Quartus for Altera (Intel) and ISE or Vivado for Xilinx. Learning HDL (either VHDL or Verilog) is a long road, and existing programming experience is usually more hindrance than help since it LOOKS like programming but it is a completely different paradigm, it is actually digital hardware design.

[ebastler]

What I need to do now is get some free simulation software,  work out how much estate I need, and get the cheapest FPGA that'll fit the hardware description.

Good plan. That might give you some insights into what FPGAs actually do and what they can be used for. Warning: There is work and learning involved. 

My idea is really simple.
I don't need the video signals,  I just need the game model to play through with random controls, then the score goes into a max circuit, the one that scored the highest out of the whole lot of testing every 100 milliseconds is what the computer does, to do the Ai.  It helps if its an FPGA because u get the "game samples" at the HZ of the machine just with the electrical delay slowing it down. (so its bloody quick!)

I don't think you have thought this through. Wouldn't your AI need to formulate some "strategies" for the controls, see how these perform, refine them etc. rather than just rely on a never-ending stream of random paddle moves? How would it feed that "strategy" back into the FPGA?

On the other hand, the "optimum strategy" for PONG is so trivial that this does not seem to be a worthwhile example for a self-learning system. "Always keep your paddle at the height of the ball", duh...

[Capernicus]

Yes, for pong its a little over engineered, but something like 2 player turbo snake (where the snakes are blocking each other in.) would suit it more, something thats hybrid reflexes - strategy close to the moment decisions is what it would be best at.  Racing would be good too.

That's amazing that 2000? "logic elements" (not that I know what I'm talking about yet.) Is enough for a sprint game and pong (From james_s's exp),  and that u can fit 1000?? whole game repeats on that little spartan,  by my early computations, that would exceed GPU performance (what I know myself) by a huge amount, but early days yet.

I have to wait and see what I get for real.

But I do realize that a big GPU will compete with a big FPGA,  and u can even use GPUS for high frame rate/output frequency tasks as well, if your very good at divvying out the instructions to the cores, u can get kilohert framerates even out of a GPU.    But it would be funny if FPGA's come out cheaper by a mile.  Industry market secrets,  but I dont know yet.

[james_s]

Well I just know that I fit Pong into a CPLD years ago, it was my first ever project with that sort of device and I never got it working quite right, but it fit in a device that was something like 180 logic blocks and it ran the attract mode. You're welcome to play around with the projects I've released, most of the arcade games I did use a 6502 CPU, and my releases are all targeted for the EP2C5T144C8 but should be easily ported to other hardware. https://github.com/james10952001

Think about the original hardware, Pong for example is something around 70 TTL chips, each of those is only a handful of gates, what is amazing is how much they were able to get out of so little hardware. Pong in particular was ingenious, it pioneered techniques like the "slipping counters" that create the ball movement. There is no computer, no code, no ROM, no memory of any sort beyond a few latches. The other early B&W games were the first uses of things like ROM to hold graphical elements, motion objects, collision detection and other techniques that went on to be staples in video game design.

[Capernicus]

Thanks alot for the link!     I love the old arcade too,   I only got a short glimpse of the B&W arcade, it died out by the time I was 8-10 or something.

200 logic blocks hey,  that's quite amazing.      I bet it was hard to get it that small tho,  I doubt my model is going to get that small, but optimization lowers cost and increases performance!
So I know what I need to do then to get this thing going good.

Can I just download those and plug them straight into a sim and run them?

[james_s]

I didn't do anything to get it that small, I just duplicated the original schematic which was already small, I didn't even use HDL in that early experiment, I used the schematic entry feature in Quartus, Nolan Bushnell did all the optimization 45 years ago when TTL logic chips cost around $10 each so there was good motivation to find tricks to minimize parts count. Part of the reason I never completed it is I discovered that schematic entry looks nice for beginners but it is a nightmare to debug and maintain, it was still an interesting proof of concept though. I'll reiterate, FPGA development is not programming, it is hardware design. Optimization isn't done the same way it is in code, it is a matter of simplifying hardware, and to some degree it requires familiarity with the internal structure of the FPGA. It's entirely possible for very tidy compact looking HDL to synthesize hardware that is a convoluted mess, while what appears to be a bloated mess of code can produce very clean well optimized hardware. It's a whole different world, which is why I mentioned that previous coding experience is often more hindrance than help. Superficially HDL LOOKS like code, but that's where the similarities end. You are actually describing a schematic, using a special language that superficially resembles a program.

Well to run it in simulation you'll need to write a test bench that generates the master clock and some control inputs but otherwise yes, more or less. Just keep in mind that in simulation you will not be running it anywhere near real-time, it will spit out a simulation of a few milliseconds of operation. Simulation is intended for debugging portions of a design, something akin to unit testing, timing in particular.

[Capernicus]

Thanks for the advice.   Respect to the old hardware wizards, including u guys oc.

I have coded my own truth table machines before,  and I am a fairly hardened beginner when it comes to hardware/electronics even with raw electricity, I actually re-invented the marx generator by accident, it was just a novel form of voltage doubler as far as I knew, it was funny when I saw it was invented along time ago! =), so I should be ok thanks.

So Ill try verilog in Quartus?

[dmills]

Personally if you have a software background I would go VHDL, verilog looks far too much like a C family language and you are likely to fall into the trap of writing software rather then describing a circuit.

Regards, Dan.

[james_s]

I use VHDL personally, it clicks better in my brain. It's strictly a matter of personal preference, anything you can do in one can be done in the other,  you can even mix and match VHDL and Verilog files in the same project. My suggestion is try them both and see which one you like.

[rstofer]

200 logic blocks hey,  that's quite amazing.      I bet it was hard to get it that small tho,  I doubt my model is going to get that small, but optimization lowers cost and increases performance!

MANY years ago, my brother worked in a bar and they had a table-top Pong game.  Inside the cabinets were the schematics so I wire-wrapped one.  I have forgotten how many chips were involved but the case was about 7"x12".  It worked well!

I sure wouldn't waste an FPGA on a Pong game when it can be built (and upgraded a bit) from a PIC 16F688 which costs $2.04

https://geoffg.net/Pong.html
https://www.digikey.com/en/products/detail/microchip-technology/PIC16F688-I-P/593003

It might be a suitable first project but I would recapture the FPGA fairly quick. 

You also need some form of A2D converters for the analog inputs.  Perhaps hanging on an SPI bus?  I like SPI a lot more than I like I2C...

[james_s]

I sure wouldn't waste an FPGA on a Pong game when it can be built (and upgraded a bit) from a PIC 16F688 which costs $2.04

It's not the same game though. You can write a Pong game in software but it will not be quite exactly the same as the original because the original didn't have any software. It is actually more nuanced than it first appears, and the original actually had a bug in the wiring of  a signal that determines the trajectory of the ball bouncing off certain parts of the paddle.

Either way it doesn't really matter, Pong will fit in a $3 CPLD, an FPGA makes a good development platform though.

[Capernicus]

So 144 (edit, oops that was inches not chip count sorry) TTL logic chips roughly estimates to 2000 logic units?

Im not sure if Ill need analogue ins yet.     Depends if I'm just making an fpga retro game ai system, or something else...

[james_s]

So 144 (edit, oops that was inches not chip count sorry) TTL logic chips roughly estimates to 2000 logic units?

It's pretty hard to make a direct comparison since the contents of TTL chips varies considerably. You can look at the datasheet for a CPLD or FPGA and it will show you exactly what is in a logic block. You can also try some very simple circuits and compile them for a particular part and see what it shows you as far as resource consumption. It gives you all the details you could possibly want.

[ebastler]

So 144 (edit, oops that was inches not chip count sorry) TTL logic chips roughly estimates to 2000 logic units?

I am not sure where you got your example numbers (the 144 chips as well as the 2000 logic units); they don't seem to correlate with anything mentioned about PONG in this thread?

A typical logic cell in an FPGA comprises a flip-flop and a configurable logic table at its input. Hence, for a first ballpark number I would estimate "one FPGA logic cell per flip-flop in the TTL chip", and "one FPGA logic cell per externally avaliable logic gate in the TTL chip". E.g. eight logic cells for an 8-bit latch or counter, and four cells for a 7400 NAND gate.

That estimate may be too low for some of the flip-flop based chips; e.g. a synchronous counter will have logic with many inputs for its high bits and may require some extra cells. On the other hand the estimate should be high for the discrete logic gates, since they can often be "absorbed" into the front-end logic of a flip-flop. So overall this should get you into the ballpark.

Besides the number of logic cells, the infrastructure to connect them may limit the density of your FPGA design. But with your PONG idea, which will mainly need local interconnects within the small PONG game units, I would not expect that to have a severe impact.

For PONG with its sixty-some chips, and assuming an average of 5 or 6 logic cells per chip, that would give you 300 to 400 cells. A bit higher than what james_s had mentioned earlier, but directionally right.

[james_s]

It occurred to me that I could just go and look at the usage. As it turns out, it seems I no longer have the initial Pong I did using the schematic layout, however I do have a Pong implementation someone else wrote in Verilog that I ported to some of my hardware so I compiled that and your 300-400 cells estimate is actually very close. I thought the CPLD I used was only about 200 cells but I could be wrong, it was not a very big one though. In this case here I used an FPGA instead, they're convenient in that they have PLLs and such so you don't need to feed the thing a specific clock frequency.


Flow Status   Successful - Thu Apr 08 22:44:34 2021
Quartus II 64-Bit Version   13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name   pong_v
Top-level Entity Name   pong_v
Family   Cyclone II
Device   EP2C5T144C8
Timing Models   Final
Total logic elements   365 / 4,608 ( 8 % )
Total combinational functions   364 / 4,608 ( 8 % )
Dedicated logic registers   163 / 4,608 ( 4 % )
Total registers   163
Total pins   10 / 89 ( 11 % )
Total virtual pins   0
Total memory bits   0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements   0 / 26 ( 0 % )
Total PLLs   1 / 2 ( 50 % )

[Capernicus]

Yes I was a bit optimisticly budgetting things,   so being about 1 gate a logic element roughly,  an adder taking a logic element up per significant bit, its not quite as fabulous as I was thinking,  but its still quite good, especially if you can shave down the significance for different variables as you need to.

So now im just drawing up my model,  i want to fit it in 100,000 LE's hopefully, (Im guestimating ill need 10,000 10 bit adders) but need to wait and see.

[ebastler]

Sorry, you lost me there. This must be a different project now than the "many parallel PONGs" you sketched earlier?

Where do the 10,000 10-bit adders come from? What do they add, i.e. where are the data they are adding being held? And you are assuming a ripple carry, right, otherwise you would definitely need more logic.

[Capernicus]

I'm not doing pong exactly, but it is a physics model the same.

INPUT    last scene image
              |
             \/
  (500 adders worth,
  to transform the scene.)   <-THIS IS WHERE PONG WOULD GO, if i were doing pong.
              |
             \/
OUTPUT next scene image.

(edit, its 500 adders (ripple carry yes) not 10,000  cause I need 20 in a row physically, for the frames in front.)  - thats what I have to fit 1 step in.  So maybe it wont quite fit,  but Ill finally know what im dealing with once i get the gate design down.

then I need to put the whole chain of frames for how long in front it looks, But that is always less than 30.
probably only 20 or even 10 would still work for me.


Its 3d vector matrix maths, inside the transform,  like in a 3d video game (opengl or directx),   but I get rid of all the multiplies and just do it with add and subtract,  I do rotation without sine and cosine and its split 360 degrees onto a flat edged polygon instead of a perfect circle.  (old school.)

Its more complex than pong,   but hopefully not much more,  I have the ordinary c version half typed out, I need to get the motivation to finish it off, and then ill see how many adders it will be.  (Its just adders and conditions, should be the whole thing.)
I dont know how complex itll be,  there could be some really great shaves in front of me,  I have to get the basic idea down first.

If I could afford a really expensive FPGA, then I could put parallel cores in,  but as it turns out Ill probably be only able to fit 1, that's what its looking like now,  but it'll still be extremely quick anyway,  well worth doing.

[james_s]

Well keep in mind the FPGA I'm using in my example here is a very old part, and tiny by modern standards. Even several years ago the entire dev board was only $13.

[rstofer]

I have posted several times that my favorite FPGA, at the moment, is the Xilinx Artix 7 (-100T variant).  That particular device has 101,440 logic cells.

The more affordable -50T has 52,160 logic cells and there are boards using the -35T with just 33,280 logic cells.

See page 3 here:

https://www.xilinx.com/support/documentation/selection-guides/7-series-product-selection-guide.pdf

This little 'stamp style' module is available in the -35T variant for $89.  If 33,000 logic cells is useful.

https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/

[Capernicus]

That breadboardable one looks cool,   if u had 3 working together ud get as much working space as the -100T varient.
Would cost $225, quite cheap indeed for ~100,000 gates,  I have to finish my plan yet, get all the main bugs out before I can know how cheap I can do this per core.   Ill be chopping off as much as I can,  the more I chop it off the more chance for multicore there is.

So 1 million gates, going by that cost would be ~$2000.   and thats what I might get,  because I'm used to buying new GPU's Im used to paying an arm and a leg anyway.   I want to get a big daddy for it, because this thing is kinda special to me.

Ill put the log of (how many cores by the fpga hz) on the name of it.   the "X" 31,  maybe it might be. =)

[rstofer]

Be careful with 'gates', 'logic cells' and other terms.  Make sure you know the exact definition as it applies to your chosen device.  'Logic cells' in particular is a marketing term used to level the playing field across logic families and vendors.  It is mythical and of no particular importance.  'Gates' is even more obscure because everything is based on the LUT (Look Up Table) which is really just a MUX and can have a lot of 'gates' involved.

Better to know how many 6 input LUTs a 7 series device has because that is about as granular as you can make your logic.  So, look at the definition of a CLB (Configurable Logic Block).  It will have a pair of 'slices' each of which has 6 input LUTs, some carry chain logic and a couple of flip-flops.

Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs

Note 1, Page 11 here:

https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

The -100T has 15,850 CLBs and that is a heck of a lot more than 1,000,000 gates.  Even the Spartan 3 1200E had more than a million gate equivalents and it's tiny compared to the Artix 7 100T.

See page 2 here:

https://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

I used the XC3S1200E for my 1130 project (the 7 series wouldn't even be invented for several years after I finished the project.  At least to the consumer grade Artix 7...

The device has 1,200,000 'gates' or 19,572 'cells'.  One way to compare the 1200k versus -100T is in terms of CLBs.  The -100T has 7,925 and the old Spartan 3 1200E has 2,168,  I told you the -100T was large.  Remember, the 1200E has 1,200,000 gate equivalents so the -100T might be talking about 4,386,000 'gates'.

It's really tough to compare devices or even figure how large any one device is.  It's better to just read the Synthesis Report and figure out how full the device actually is.  See attached
 
Note that my IBM1130 project uses around 10% of the flip-flops and just 24% of the LUTs.  That's for a complete system including CPU, Card Reader, Line Printer, Disk Drive, Keyboard and Selectric Typewriter.  The Artix 7 is more than 3 times as large.

[gnuarm]

"Logic cells", "gates", "LUTs"... they are never an accurate way to compare FPGAs because FPGAs are not just any of those things.  Even worse, the logic features of each family may or may not be particularly usable in your design, so if counted in the "logic cell" or "gates" count it may or may not be useful counts. 

The bottom line is to test your design against the various chips.  This is not so much different from using standard benchmarks to compare MCUs.  The only meaningful benchmark is your application. 

[Capernicus]

How big a computer is a IBM1130 -  thats nifty that u got that working, so u could fit about 4-5 more cores on it if u wanted?
That would be great if if its true!    I hope your right,   but if you look at this video he shows that the adder takes up ~80 of the "dots" and theres only ~10,000 of them there,   so that would come to as far as I know about adders granular 64 gates for a 32 bit adder,   but I spose I dont know how many bits this adder is,  but its taking up a fair bit of space, theres only room for ~200 here, it looks like.

(at 12:40)



But if these LUTS are 6 input, that means they are 64 row, but I bet if the compiler is any good it could put more than one granular gate into the same LUT? But I guess maybe its not always good to rely apon the software to do things, because sometimes its not so good.

But that doesnt make sense, if the LUTS were larger than 2 op gates, then there wouldnt be 80 dots there used space...   doesnt look large from this standpoint.  But maybe this isnt just a ripple carry adder and theres more there than that,  and hes being a bit cryptic about it, not sure.

So I'm not sure what I'm doing but Ive got Intel Quartus 64gig download on the way, then Ill see if I can get something emulating.

but why the hell is it a 64gig download...  that is terrible!!!