Not sure where to start. There are, however lots of schematics on the net for Z80 based systems. If you'll excuse the fact that I haven't played with one for 20 years (though there are increasing numbers accumulating in the parts bin so I really should put together a few simple systems sometime) here are some random thoughts.
CP/M is
mildly tricky on a Z80 because it wants RAM at low addresses, unfortunately the Z80 pushes you towards ROM at low addresses because reset pushes 0000H into the program counter (actually that's pretty much all reset does) so you tend to want ROM there just after reset.
A minimal Z80 system can be built with a static RAM, a ROM and a few latches for a bit of memory mapped I/O. Depending on the RAM&ROM size you can construct a basic address decode with something like a 74LS138 (to decode 8 blocks of 8K) or half a 74LS156 (to decode 4 16K blocks). Using the former as an example you connect the top three address bits (A
15, A
14 and A
13) to the A
2, A
1 and A
0 inputs and MREQ to one of the active low enable inputs and that gives you 8 select signals which you can connect to the active low chip select lines on your EPROM and RAM. Obviously if you have one 8K EPROM and one 8K RAM you'll have six unused selects. These can be used for "memory mapped" I/O.
The INMOS RAM chip you mention is a 4kx4 so you need two of them one connected to D
0 to D
3 and one to D
4 to D
7 but really it's a lot simpler to find a 6264 somewhere.
True bank switching is very easy (but I'd get a system without going first) - I use two 74LS189 16x4 SRAMs to create a 16x8 RAM. The address inputs are connected to A
12-15, the 8 data out lines become the expanded address bus lines A
12-19. The 8 data in lines connect to the data bus. CS can be tied low and WE needs to be gated from IORQ, an I/O address of your choice and the CPU WR line.
The beauty is that (apart from the address decode) you basically just need the two RAM chips to expand the address bus to 20 bits - to program remember that "OUT (C), A" is really "OUT (BC), A" so you use the top 4 bits of the B register to select which RAM address to write to - no need for otherwise rather complex gating to select between address lines depending on whether you're programming or using the bank switch.
The snag is that it's static RAM so will start up with random contents - thus you need to design you hardware such that following reset your ROM takes precedence until you flip a bit to enable the bank switching (after programming the mapping RAM, obviously).
have the sources for CP/M, I just need to compile them, which shouldn't be too hard
You need to write a BIOS to match your hardware (BT, DT)
Or build your hardware to match an available BIOS.
You pretty well need 64K of RAM for CP/M
Should I have A0-A3 going to the SRAM, then A4-A15 going to the EEPROM, with A4 also going to CE on the EEPROM? Or something like that?
Hmmm, definitely a bit of confusion here about how the address bus works.
Sticking with "memory" (ROM&RAM) the low order address lines go in parallel to all the devices (typically A
0 to A
11 or A
12) the high order address lines are then used to derive select lines which pick just
one of the devices for a given address. For ROM&RAM you also need to gate in the MREQ line to make sure that the (active low, usually) select line is only active when MREQ is active.
For I/O you use the same scheme except that oficially you use IORQ and A
0 to A
8 to select from 256 possible I/O devices - however there are really 64K I/O addresses because the OUT (C), reg instruction actually puts the contents of the B register on the top 8 adfdress lines.