More on the Gigatron 4 layer PCB for EMC compliance testing. Swapping the inner and outer plane layers, experimenting with KiCAD and investigating several issues with the tool.
Talk on gerber generation, PCB checklists, PCB design for manufacture, PCB stackup, and uploading to JLCPCB for 4 layer manufacture.
Hello. What's going on? Why is the video unavailable?
This happens occasionally... Dave finds something in the video he wants to fix, so it is taken down and will be re-uploaded when he's done.
Could take a couple of hours to a day or so ... but it will come back.
As I mentioned on a youtube comment my guess about the unconnected pad is that the zone doesn't go through the center of the the pad so isn't considered connected.
When this has happened to me I just run an extra trace just in case.
This happens occasionally... Dave finds something in the video he wants to fix, so it is taken down and will be re-uploaded when he's done.
Not this time.
It never finished processing after a day, still only 360p. Pointless watching in 360p only. Something weird is going on with Youtube, reports of similar issues with other creators.
Reuploading to try and fix it.
This happens occasionally... Dave finds something in the video he wants to fix, so it is taken down and will be re-uploaded when he's done.
Not this time.
It never finished processing after a day, still only 360p. Pointless watching in 360p only. Something weird is going on with Youtube, reports of similar issues with other creators.
Reuploading to try and fix it.
Was playing at 720p for me last night?
Re-uploaded and now processed fine, new video embedded above.
This happens occasionally... Dave finds something in the video he wants to fix, so it is taken down and will be re-uploaded when he's done.
Not this time.
It never finished processing after a day, still only 360p. Pointless watching in 360p only. Something weird is going on with Youtube, reports of similar issues with other creators.
Reuploading to try and fix it.
Was playing at 720p for me last night?
A few others reported also seeing processed version, but most couldn't and Youtube video manager never showed it as not processed yet.
Is this video not listed on purpose?
Is this video not listed on purpose?
Youtube screwed up and would not process it, I had to reupload.
I once heard that emissions reduce by 6dB for every 2 layers added. Really looking forward to see if this is similar. However, more than half the fails I see are from common mode radiation from cables and cable shields. I hope the design of the EMI test takes this into account; and, reveals good ways to avoid these fails.
Swapping continous internal power layers to top & bottom may be impractical. But, if a clock oscillator has a high frequency harmonic EMI fail, perhaps this could be done locally just at the xtal?
I see you are starting to warm up to Kicad
I see you are starting to warm up to Kicad
I was having the same thought.
If the developers are watching they might get terrific feedback from someone with credible experience. There can't be many Kicad users coming to Kicad from a dominant industry package direction.
I realize that you can't please everyone with your videos, but this one just put me to sleep 
If you don't like it then don't watch it - and feel free to keep it to yourself. You aren't likely to influence Dave on his subject matter, style or content by being negative. You
are likely to piss him off more and more for no good reason.
Dave doesn't need to know your personal opinion about particular videos. Everything he needs to know is encompassed in the stats he gets. If, for some reason, he wants to know more information, I'm sure
he will ask (as he has in the past). At the time of writing, by just looking at the like/dislike ratio of
this video, for every 1 person who did not like it, there were
75 who
DID.
I really enjoy watching videos that are the result of a "What if ...?" question. They often answers basic questions that we all ask, but no one gets around to actually test.
If this board ever get to a EMC test-house and an A to B comparison to the other board will be made, my guess is that some of the dominant radiated frequencies will be attenuated.
But I see a weakness in swapping the layer order. The edge is still open and even though making a fill on the top layer and stitching it to the button layer have addressed this there is still a slot between the two fills. This slot is very much comparable in size and shape to the opening on the board edge, so my guess is that this is where the board will radiate from. Luckily this can easily be circumvented with the changes Dave made. In an ideal world, the two power planes can be (AC) shorted by multiple small capacitors preferably each placed close to a via and at the same rate as the via stitching. This deviates somewhat from "just swapping the layer order", though.
Just my $0.02
/Sverre
I really enjoyed this video as a neophyte PCB designer who is reasonably familiar w/ KiCad. Watching Dave, who is an expert on PCB design but is still learning KiCad, has taught me quite a bit about the sorts of workflow patterns that an expert would expect to be using and how to get things done in KiCad. Great video!
mmh where is the link to the previous video you mention at the beginning???
edit:
oh, ok video #1176
I once heard that emissions reduce by 6dB for every 2 layers added. Really looking forward to see if this is similar. However, more than half the fails I see are from common mode radiation from cables and cable shields. I hope the design of the EMI test takes this into account; and, reveals good ways to avoid these fails.
Swapping continous internal power layers to top & bottom may be impractical. But, if a clock oscillator has a high frequency harmonic EMI fail, perhaps this could be done locally just at the xtal?
I've never heard of getting 6dB attenuation for adding extra layers. It is all about the currents flowing through the layers. If you have a high speed signal running on the top layer and a ground plane on layer 2 then the HF return current will run through the ground layer along the trace. So in theory it shouldn't matter whether the ground plane is on the outside or the signal is at the outside. The magnetic field you pick up from the signal should be in the same ballpark. For shielding to work it should be connected at points of the circuit which have no current running between them.
I've never used Kicad, but that last DRC failure that won't go away, couldn't it be because the center of the pad is slightly outside the polygon, and that makes Kicad think that it is not connected to the plane?
I've never used Kicad, but that last DRC failure that won't go away, couldn't it be because the center of the pad is slightly outside the polygon, and that makes Kicad think that it is not connected to the plane?
I'm certainly no KiCad expert but I had a look at 36:08 where you get a view of the entire edge with connectors. There's no exception to contradict your theory. It's certainly consistent with the changes Dave was making pulling back the plane from the edge. It shouldn't be too hard to test it.
If Dave doesn't confirm it, how confident are you?
If the ic pins have the same pad size on all four layers then all that is needed is to rename the gerbers. Done.
I think its credible for radiated emissions to go down where the emission is radiating from an unintended current loop on top or bottom. Moving them to inner layers effectively shields the current loop. Down side is that conducted emissions on power lines or attached cable shields may go up. The proof will be in the test result.