Anyone tried the Hantek LA5034 logic analyzer?

[slburris]

As with most things Hantek, reviews from actual users seem to be
few and far between.  So, anyone have or tried this:

http://www.hantek.com.cn/english/produce_list.asp?unid=44

Seems to be in the same market space as the Intronix LogicPort.
500Mhz sample rate, on the fly data compression, for about $300.
There seem to be a lot of rebrandings of this unit floating around.
I've tried to figure out who the real maker is, but haven't made much
progress.  Is it Hantek?  Who knows?

Scott

[mikeselectricstuff]

Only 2k sample depth - pretty useless.

[slburris]

Only 2k sample depth - pretty useless.

Compression, i.e. only store transitions instead of the same data over and over again at each
sample clock.

The Intronix Logic port has only 2K but it does compression as well, and people who have it
and written reviews seem to really like it.  My understanding is the Intronix internals are
an FPGA and the capture memory is internal block RAM in the FPGA -- that's how they hit
500Mhz.  It wouldn't surprise me if the Hantek is similar.

Now if you are sampling a processor data bus and can't set up a reasonable trigger condition,
I can see how compression would fall flat on its face.  I suspect most of my applications would
do fine with compression, as my current workhorse LA is a Tektronix 1240, which is 100Mhz
with a 2048bit depth memory, no compression.

Scott

[dimlow]

 I have one, the software is crap to say the least, used it for a day or two then i have never used it since. id say stay away. There are much better LA's out there for just a little more money. Maybe they have improved the software since i last checked. At one time i was working with the developer to improve the software and we did get some improvements. But after a time their interest in my suggestions dipped. My interest in the LA dipped so low that i never use it any more.

[dimlow]

@Shafri, you have the wrong idea on compression on a LA. For example you may be sampling at 100Mhz, this will quickly fill the LA's memory. You may in fact only be looking at a 10Mhz bit stream. So you will not in fact see a lot of that bit stream because you need to sample at 100Mhz or you may miss some transitions in the stream. So here comes LA compression. the LA still samples at 100Mhz but now only stores in memory the transitions it finds and when they happened. This way you get to see a lot of the data and still you can sample at 100Mhz.

I cant really explain things that well so i will go hunting for a link for you now.

BRB.

[armandas]

Only 2k sample depth - pretty useless.

Compression, i.e. only store transitions instead of the same data over and over again at each
sample clock.

yup compression can help alot (or abit). but since i learnt a bit of compression basic long time ago, makes me question if the compression is doing any good if say, its probing an already compressed like data stream? IMO it will be very difficult day for the FPGA to do the job if its feed with such random binaries.

It looks like you're confusing waveform compression with data compression. Storing transitions wouldn't help much if the signal is alternating frequently (like a clock), but it's good for short bursts that are long time apart.

You may want to check Dave's video about logic analysers.

[dimlow]

here is a nice document that explains it.  take a look a fig 3

http://www.eetindia.co.in/STATIC/PDF/200705/EEIOL_2007MAY02_POW_EMS_TEST_TA_01.pdf?SOURCES=DOWNLOAD

[dimlow]

@Shafri. I think you need to eat a little bit of humble pie. Read the doc i posted, you will understand then, Compression in a LA is not data compression. More of a time/transition storage. No actual compression algorithm is run on the data. It only stores data when it needs to. It does not compress the whole datastream.

[Time]

Lets not argue semantics here.

[dimlow]

armandas is sort of correct correct when he talks about storing transitions of a clock, when using the LA i dont ever look at the clock, i may trigger of it. But most of the time the clock does not interest me. i would be looking for a combination of signals, maybe an address on the address bus and trigger from that.

When using the Hantek i found the 2k was fine, i don't think its 2k memory but in fack 2k samples ie 2kx32bits, so when using "compression" there is plenty to see.

As for the 10Mhz data at 100Mhz Sampling, that has nothing to do with Hantek, that was just me trying to explain. The Hantek can sample at 500Mhz. What i was trying to say, was basic sampling theory, if you look at a 10Mhz clock with 10Mhz Sampling you are going to miss transitions. so you sample 10 times faster to see them ie 100Mhz. If your sample at 100Mhz and storing every sample you will use a lot of memory space. This is were "compression" comes in handy. On the other hand if you have a clock signal to trigger the sampling from then yes you can sample at 10 Mhz because that's when the sample will be stored. The Hantek is "OK" but i just did not get on with the software. A lot of the time i found myself playing with the software and not really getting on with the job in hand. But in the end it does what is says on the packet.

Yes very much looking forward to the scope getting fixed, Been teaching my sons how to program pics and have been trying to show them the output on a scope so they can see what's happening.

[slburris]

For the Intronix, the compression takes multiple consecutive samples that
are the same and stores it as a bit value (0 or 1) and a length that encodes
the number of samples.  Basically it's Run Length Encoding:

http://en.wikipedia.org/wiki/Run_length_encoding

So it's a form of compression, however you want to debate the semantics.

Don't know what the Hantek does, but I'd hope it was similar.

If you have a transition on every sample clock edge, the compression won't do
any good, otherwise it increases the effective storage space.

Scott

[slburris]

OK, so let me pose a different question.  I you want 500Mhz capture and a large
buffer, what can you get?

The speed takes out all of the stream over USB and use your computer memory
for buffering devices, the capture buffer size takes out the Intronix and wannabees.
Many of the cheapy LAs don't allow you to set the logic threshold either.

So what's left?  Probably something the cost of a small car from Brand A or Brand T
I would think. 

Scott

[dimlow]

OK, so let me pose a different question.  I you want 500Mhz capture and a large
buffer, what can you get?

Nothing, Unless you have large wedge of cash

[mikeselectricstuff]

OK, so let me pose a different question.  I you want 500Mhz capture and a large
buffer, what can you get?

The speed takes out all of the stream over USB and use your computer memory
for buffering devices, the capture buffer size takes out the Intronix and wannabees.
Many of the cheapy LAs don't allow you to set the logic threshold either.

So what's left?  Probably something the cost of a small car from Brand A or Brand T
I would think. 

Scott

If you want 500M capture and a large buffer the answer is wide RAM.
However most of the time a logic analyser will not be being used at full speed, so large RAM at lower speeds would be very much more useful than a fixed 2K. Deep memory is most useful for things like decoding serial protocols, where high speed is not a major factor.
The problem with not having much RAM attatched to the FPGA is that the timing on USB, even USB2HS is unpredictable, and 2K is nowhere near enough to ensure no buffer overrun. Adding some cheap RAM would make a USB analyser way more useful.
A 4Mx16 133MHz SDRAM is about $1, once you account for address setup overheads, you can get maybe 100MHz sustained transfer. A single 16 bit wide SDRAM could therefore give you 200MHz sampling of an 8-bit bus.

[alm]

However most of the time a logic analyser will not be being used at full speed, so large RAM at lower speeds would be very much more useful than a fixed 2K.

Only if you use ancient stuff or low-end 8-bit micros. The top speed for a streaming USB bulk transfer logic analyzer is 24MS/s. If you want any timing accuracy at all, you're limited to <= 5MHz or so. Tons of interfaces are faster than that, even in the low-end embedded world. Both types have their uses, but I wouldn't call the slow 'unlimited' depth type very much more useful, although price/performance might be better.

The problem with not having much RAM attatched to the FPGA is that the timing on USB, even USB2HS is unpredictable, and 2K is nowhere near enough to ensure no buffer overrun. Adding some cheap RAM would make a USB analyser way more useful.

USB is nowhere near fast enough for 500MS/s, these types of logic analyzers are usually designed to just fill the internal memory, stop acquisition and transfer. So buffer overruns are by design.

A 4Mx16 133MHz SDRAM is about $1, once you account for address setup overheads, you can get maybe 100MHz sustained transfer. A single 16 bit wide SDRAM could therefore give you 200MHz sampling of an 8-bit bus.

You'd probably need a more expensive FPGA to handle SDRAM. You might also need more than the 2k buffer to counter the latency. For 32-bit wide access, you would need tons of chips. And I'm skeptical about the $1 figure if you have to buy it in commercial quantities (can't just get them from a dusty shelf in the local computer store).

I don't really see the appeal of this over the Intronix Logicport, which is well known and has proven itself. I would take a hard look at the software, because most software from low-budget Chinese companies is pretty bad. The Zeroplus software was absolute crap last time I looked at it. I also wonder if it has the same features (both timing and state analyzer mode, adjustable logic thresholds). Another interesting option is the Open bench logic sniffer, it's only $50 or so and the software is maturing quite nicely. It doesn't do 500MHz (200MS/s for 16 channels), but has more RAM. The software is maturing quite nicely.

[dimlow]

Just for fun, i opened up the Hantek LA5034. Not a lot inside and a lot of the chips are scrubbed out.




You can see the full size Album of photos http://picasaweb.google.co.uk/Dimlow/20100930LA5034#

[slburris]

Why do they insist on scratching stuff out?  It's not that hard to figure out.

U10 is an EPCS4 4Mbit serial configuration flash from Altera.
OK, so the FPGA is highly likely to be an Altera chip.  J2 is the
JTAG port, so it would be trivial to read the IDCODE of the FPGA
and know exactly what it is.

It's probably a Cyclone 3 chip, maybe an EP3C16?

Serial # 35?  Wow.

You know, if you could get this hardware cheaply enough, you could
solder in a JTAG header and use it as a low cost FPGA board instead of
a logic analyzer.  It looks like the configuration memory is in the JTAG chain.

Scott

Scott

[mikeselectricstuff]

The problem with not having much RAM attatched to the FPGA is that the timing on USB, even USB2HS is unpredictable, and 2K is nowhere near enough to ensure no buffer overrun. Adding some cheap RAM would make a USB analyser way more useful.

USB is nowhere near fast enough for 500MS/s, these types of logic analyzers are usually designed to just fill the internal memory, stop acquisition and transfer. So buffer overruns are by design.

Obviously, which is why you need more RAM in the analyser, as the USB transfer rate becomes effectively irrelevant once you can't stream continuously.

A 4Mx16 133MHz SDRAM is about $1, once you account for address setup overheads, you can get maybe 100MHz sustained transfer. A single 16 bit wide SDRAM could therefore give you 200MHz sampling of an 8-bit bus.

You'd probably need a more expensive FPGA to handle SDRAM.

Probably not much more - chances are you alreay have close to enough pins, so maybe one package size jump. The SDRAM setup is only a few cycles at the SDRAM clock speed, and those cycles give you a pretty decent size burst transfer, so you're still well inside low-end FPGA territory.

You might also need more than the 2k buffer to counter the latency. For 32-bit wide access, you would need tons of chips. And I'm skeptical about the $1 figure if you have to buy it in commercial quantities (can't just get them from a dusty shelf in the local computer store).

4Mx16 $1.31 in 100x at Digikey

The point is I think a USB analyser with a decent amount of internal RAM would be a LOT more useful for a relatively small build cost increase.

[Mechatrommer]

The point is I think a USB analyser with a decent amount of internal RAM would be a LOT more useful for a relatively small build cost increase.

i'm assuming, they try to get the same spec as other competitors (smaller ram version) and put the price at some reasonable level. once they bought the several cent more expensive bigger ram, they will increase the products price by hundreds, or even thousand! thats why its suck! just my assumption.

[alm]

The point is I think a USB analyser with a decent amount of internal RAM would be a LOT more useful for a relatively small build cost increase.

I agree that it would be much more useful. Not so sure about the small increase in cost at 500MHz, but if any of the manufacturers can pull it off, I certainly won't complain.

[slburris]

Looks like you can pick this up in the US for $232 here:

http://www.thefamousbrandsoutlet.com/test-measurement-instruments/pc-based-usb-logic-analyzer-la5034.html

But if the software still has issues, it's not a bargain over the Intronix.

Scott