Nice find! I just glanced at the manual, the 2553 seems to use a DAC and a code value from the CPU to set the desired output voltage, but it uses an FPGA to shape the code run up, and then uses an ADC in the feedback loop to servo the FPGA/DAC combination to keep the setpoint. Cool and very similar to the Jim Williams app note 86 using a 24 bit adc to servo a 20-bit dac.
http://cds.linear.com/docs/en/application-note/an86f.pdf
Their code comparator is inside the FPGA and it also does code shaping on code changes from the main cpu and in the feedback loop, to control rise times, overshoot, etc.
EDIT: the best thing about this architecture is that it's only dependant on the accuracy and stability of the 24-bit ADC and it's reference. So an expensive 24 bit ADC with < 1 lsb INL/DNL and a stable reference can correct for a cheap, non-linear DAC, cheap non-precision output op-amps, and less than perfect output drivers.
EDIT 2: This application probably doesn't even need the ADC to be as good as I said above, since they only have 5 decades