Have you seen worse reference layout than this?

[Yansi]

Just a small rant... planned to use a small DC/DC converter from ROHM. Checked Mouser for price and stock and wow... Look at this beast! Hell!  1.5MHz switching supply, routed that way. Just cannot believe that...

Post some more from your collection of sh*t layout reference/evaluation boards, if you have some!

[tom66]

Don't see a problem with it - planes are large so inductance will be pretty low. Layout is done right with loops kept either small or low-inductance, and it's pretty typical for ref boards to be made this way - allows for mods to the board e.g. bigger inductor or more caps by scraping soldermask off and for best thermal performance (they want the chip to look as good as possible.)

[stmdude]

    That seems pretty standard for DC/DC reference designs..

In fact, this looks _very_ similar to the output from TIs WeBench tool..

[Yansi]

Sorry, but that layout is nowhere near good enough.

In the datasheet of the device, there is this version of layout, which is purrfectly acceptable. Anything else like the above is not.

It might work on that board, but have you heard about EMC and such? 

[stmdude]

It might work on that board, but have you heard about EMC and such? 

That's typically not something that's taken into account on a dev-board

[Yansi]

There might be a bit of truth on that. But it's not an excuse. Should be very f*cking easy to conform to the datasheet layout. It is really horrible and ignorant what the layout person has done on that board. 

[wraper]

There might be a bit of truth on that. But it's not an excuse. Should be very f*cking easy to conform to the datasheet layout. It is really horrible and ignorant what the layout person has done on that board. 

Actually there is not much difference compared to datasheet layout. Capacitors are rotated differently, but all of them are connected directly to the solid ground plane on 4 layer board.

[steverino]

Yansi, for the benefit of the ignorant like me, can you explain why the layout is bad?  I hope to learn something.  THanks!

[Ian.M]

The only question is: Where does the feedback track on the underside from the via to the left of C01,C02 to the via to the right of RFRA run.  If it splits the ground plane in the wrong place, it could be an issue.

@wraper:  Why do you think its four layer?  I strongly suspect its only double sided.

[Yansi]

Why it is bad? Because this is a 1.5MHz switchmode supply. ANY parasitic inductance is a potential PROBLEM (not so much at low currents though), but what is a bad problem, is the overall area of the current loop. (The loop area is what considerably contributes to the EMI)

What is particularly bad (and absolutely unnecessary) in the layout in post #1, is the ground connections from the components being connected through vias to inner/bottom layers. WHY?! Even the datasheet suggest a simple single-layer place-able layout. Then you can ground the whole DC/DC nest with vias in a SINGLE point, to significantly decrease noise induction in the ground plane below.

I'm currently designing something with this chip, so you can look, how the layout should look like more. It is only a prototype single-piece design, still I take it as my responsibility, to make the layout as best as I can. No excuses being it dev-board or not.

[Yansi]

Compare the current loop areas. Green one is where the current flows when switch is ON, blue one is switch OFF.

Any wire length extra in those loops will contribute to more EMI issues.
Badly placed  input decoupling cap also stresses the power switch mosfet inside the IC, as there is unnecessary parasitic inductance in the circuit.

What bothers me is how can someone fuck up so simple pcb layout.

The importance of good layout increases steeply with more current in the circuits. This is only a 0.5A DC/DC, so it might be more tolerant to such factors as bad layout, but it definitely is not a good design practice in any way.

Note: Especialy for higher current applications, also the loop consisting the mosfet, diode and input cap has to be the smallest possible, because this loop contributes to a parasitic inductance, which then stresses the mosfet with overvoltage on switchoff.

[Scrts]

It's made for you to easily modify the board, change components frequently, solder wires around, etc.

Of course they could do the smallest design ever, keeping everything packed and do 4-6 layer board, but again - that's not the intention.
 

[Yansi]

My goodness. Where do you see those 4 or 6 layers in my layout?  It needs only two. (and by the way, the dev-kit really is 4layer and still piece of layout crap).

Frequent changing of components can be done on either layouts.  Still its only a very poor excuse.

[tszaboo]

It is bad. Loops are big. But probably the worst is that you dont have any via for the GND pin. At least the sense is away from the switching node.

[Koen]

What is particularly bad (and absolutely unnecessary) in the layout in post #1, is the ground connections from the components being connected through vias to inner/bottom layers. WHY?! Even the datasheet suggest a simple single-layer place-able layout. Then you can ground the whole DC/DC nest with vias in a SINGLE point, to significantly decrease noise induction in the ground plane below.

Interesting; where would you tie this block GND to the GND plane ?

[DimitriP]

So, to summarize,
the $31.25 demo/evaluation  board has a unacceptable production layout for the $1.47 part.
There is a reason there somewhere but incompetent PCB design ability is most likely, not it.

[wraper]

The only question is: Where does the feedback track on the underside from the via to the left of C01,C02 to the via to the right of RFRA run.  If it splits the ground plane in the wrong place, it could be an issue.

@wraper:  Why do you think its four layer?  I strongly suspect its only double sided.

Look on the board one more time. Internal layer is obviously seen (darker areas around the holes). And what it splits FFS?  There is no high current path in the GND to the chip.

What bothers me is how can someone fuck up so simple pcb layout.

It's made so you can easily access everything. They could pack all of the closely, but then what's the point to do this, making customer's life more difficult?
And now let's see how easy it would be to probe everything with oscilloscope here:

[Yansi]

Some people seems can only argument using stupid excuses.

[wraper]

Some people seems can only argument using stupid excuses.

And some people cannot distinguish 4 layer board form 2 layer board but yell about split GND.

[Yansi]

What is particularly bad (and absolutely unnecessary) in the layout in post #1, is the ground connections from the components being connected through vias to inner/bottom layers. WHY?! Even the datasheet suggest a simple single-layer place-able layout. Then you can ground the whole DC/DC nest with vias in a SINGLE point, to significantly decrease noise induction in the ground plane below.

Interesting; where would you tie this block GND to the GND plane ?

Near the output cap ground, as there's the point of lowest impedance for the output (and it's also the  place you want to reference the output sense or the IC gnd pin respectively. But in a tight layout with almost point-like ground it doesn't matter if the GND via is milimeter closer to this or that). It would be best then to bring bothinput leads both direct to this circuit block, which usually should not be much of a problem.

[Yansi]

Some people seems can only argument using stupid excuses.

And some people cannot distinguish 4 layer board form 2 layer board but yell about split GND.

What excuse will you bring now?

It IS a 4layer board.  Never said it is not.

[wraper]

It IS a 4layer board.  Never said it is not.

Sorry my bad, had read the post from another poster and thought that was yours.

[T3sl4co1l]

Conspicuous lack of vias around the chip GND and diode GND...

It's small so it doesn't really matter though.

On a related note, I've tested the LTC3810 dev board and it makes a horrendous noise, i.e. tens of volts worth of ~ns spikes from switching.

Tim

[rs20]

I think it's worth making a few corrections -- showing current loops that go through the inductor is a bit misleading. There are two alternative ways of explaining why this is misleading:
- The two loops are out of phase with each other, so even though both loops emit EMI, they largely cancel in practice
- More simplistically, the current through an inductor is (mostly constant).

For this reason, I believe is more accurate practice to consider the currents in such a system to be a superpostion of:
- A pure AC waveform circulating back and forth through Cin1, U1, D1 loop, plus
- Some irrelevant near-DC flows through LX

Of course, the current flow through LX is not pure DC, but it's typically orders of magnitude below the AC loop, especially in CCM. Now, the ground path from D1 to Cin1 is indeed pretty torturous, I agree with that. However:

I'm not so sure about this, but doesn't a solid ground plane go a long way to cutting down EMI here? The aforemention AC flow can exist as a mirror image in the ground plane below, and this means the EMI is actually going to be fairly minimal? Maybe? Open to correction on this point.

So although rotating Cin1 so that it has a no-via path to D1 (instead of that pointless island of ground) seems like a sensible optimisation, I'm really not convinced that this is a big deal, nor that this 4-layer design would actually perform worse than a sensible single-layer design (not a fair comparison of course, but worth keeping things in perspective nevertheless).

[T3sl4co1l]

I'm not so sure about this, but doesn't a solid ground plane go a long way to cutting down EMI here? The aforemention AC flow can exist as a mirror image in the ground plane below, and this means the EMI is actually going to be fairly minimal? Maybe? Open to correction on this point.

Overall, if there's no ground-loop voltage between sides of the boards, or terminal connections anyway, and there's little to no ripple carried out of the in/out ports (i.e., they are well filtered -- you'd probably need an extra LC filter to meet regs), then the board as itself probably isn't bad.

It could be a LOT smaller, and the vias will need to be in the right places to avoid ground loops in that case.

So although rotating Cin1 so that it has a no-via path to D1 (instead of that pointless island of ground) seems like a sensible optimisation, I'm really not convinced that this is a big deal, nor that this 4-layer design would actually perform worse than a sensible single-layer design (not a fair comparison of course, but worth keeping things in perspective nevertheless).

Yeah, at this power level, it doesn't really matter.  A converter swinging tens of volts and several amperes (and up) is where you get into interesting territory, especially if the designs follow the cookbook to a tee: lots of switching noise and never a snubber in sight.

Tim