Why can't they just stack dies to make a 3d chip?

[Beamin]

Obviously if something sounds so simple and nobody's doing it, its because the world is full of idiots and you are smarter then everyone else like Elizabeth homes and the guy that pre mixed the oxygen and acetylene in one tank, so convenient, welds faster then the speed out sound!. No surprise he was trying to weld a fart can on to his old honda and she can't get her phone to charge. 

I would think they would make a die and in-between have a buss layer that interconnects all the parts. Cooling might or would be an issue but that could be done with cooling or integrated cooling or bus layers. I think in the way future instead of 2d silicon it will be a 3d lattice with impurities making up the transistors. By then we could have machines that are made from cells like the body each doing its part and able to change functions like stem cells. A few atoms of anti mater power each cell.

[GeorgeOfTheJungle]

The power density in a modern CPU is higher than that of a nuclear reactor. The reason CPUs have to throttle down is because there's no way to evacuate so much heat quickly enough. And the raspberry Pis mount the RAM soldered on top of the CPU. Or at least they did so in the first RPis, may be not any more. No wonder it overheats all the time at full throttle.

[rfeecs]

They already do:
https://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit

As of the 2010s, 3D ICs are widely used for NAND flash memory in mobile devices.

[Gyro]

The Broadcom core chip in the Raspberry Pi stacks the RAM on top of the CPU (at least the earlier ones, don't know about the latest).

[filssavi]

It is already done (kinda) in some sectors, FPGAs and GPUs and flash mostly.

In the first two it is 2.5d, where the dies are soldered on top of an interposer which is nothing more than a silicon PCB, it is a dumb large die with only wires (no transistors), it is used for die to die interconnects with weary wide busses (like kilobits wide) to other FPGA regions of to HBM memory

NAND flash is true 3D instead with up to 96 layers of memory in some cases (and that is the only true 3D if in wide use)

It is a very active area of research, however manufacturing of through silicon Vias is still very hard, and the thermal constraints only make matters worse

Both AMD and intel are moving towards multi die with the already out Ryzen and intel announced foveros technology ad they gradually accempt that moore’s Law is dead

[Kilrah]

The Pi 1 and 2 did stack the CPU and RAM but later models don't becasue as mentioned the CPU generates too much heat for that to work anymore.

But yeah commonly used for NAND Flash.

[filssavi]

A distinction must also be made between what Flash etc does, which is true 3d IC, and the Raspberry (and older smartphones iPhone 4 and 5 era)...
that is called package on Package, where a fully packaged ram chip is soldered onto a fully packaged processor. This is a completely different process, the dies are fully normal planar cmos ICs, the only difference with normal BGAs is that on the bottom IC’ PCB (i’m Talking about the pcb inside the package, not the motherboard) has pads on top that connect to the upper IC, as opposed to only on the bottom,and possibly a recessed cavity for the die.

[Kilrah]

Sure, but the point is that even that is difficult and can't be used that much anymore due to thermal constraints, and real silicon 3D structures are likely even much less feasible with similar component types...

[Marco]

Mostly it's not worth it for logic. You could embed heatpipes or microfluidic channels inside the stack to deal with the heat, but no application can pay to make it worth it. More interconnect bandwidth is nice, but not nice enough. Maybe the NSA uses it

So for now stacking is used mostly for memory, where generally only small parts of the silicon are operating so the power doesn't matter. For memory it allows you to use a single massively parallel bus connected vertically through the stack with TSVs, which is nice enough. For lower power processors (ie. mobile phones) these can then be directly mounted on the processors, for high performance (desktop CPU/GPU) on an interposer so they don't impede cooling.

[mariush]

They do ... see for example HBM memory ... 2-4-8 dies on top of a controller die ... then stack gets soldered onto an "interposer" silicon die with micro solder bumps or whatever they call it.
Theres also hyper cube memory , there's NAND chips with up to 96 "layers" these days ... there's controllers  with dram stacked on top

They make the HBM at 14nm+, they make the gpu die at 12.14nm and the interposer die is 45-65nm (basically just a bunch of traces connecting the gpu die to hbm memory

problem is the high failure rate (one chip is bad, you lose the stack sometimes) and there's thermal considerations... uneven heating of the stack... the die on top gets cooled better while the dies at the bottom will be hotter.

Intel's also working at a design where the subtrate is only on the edges of chips making it cheaper to manufacture.

[SiliconWizard]

As said, they already do.

Some preliminary reading:

https://en.wikipedia.org/wiki/Through-silicon_via
http://www.3d-plus.com/

[excitedbox]

I hope at some point they start laser drilling horizontal head ducts through the chips and use them as heat pipes to carry heat away. Either that or lowering the amount of heat generated seems to be the only way to lower the temperature of the chip enough to make it possible to truly make 3d chips.

Imagine them making big solid copper or silicon traces in a grid pattern across the die and running coolant through them. It would probably have to be a high boiling point liquid to keep it from expanding and cracking the chip from the internal pressure.

[SiliconWizard]

Indeed, heat management can be a big issue for stacked dies.

[David Hess]

I hope at some point they start laser drilling horizontal head ducts through the chips and use them as heat pipes to carry heat away.

Heat pipes would be ideal however they have power density limits which high performance ICs passed long ago which is why you see multiple heat pipes used in parallel and attached with a massive heat spreader.  Above a critical limit of heat flux, the fluid inside the heat pipe boils instead of evaporates lowering surface area and raising thermal resistance in a positive feedback loop resulting in failure of the heat pipe.

This is also why you do not find planar heat pipes attached to high power density heat sources.

Imagine them making big solid copper or silicon traces in a grid pattern across the die and running coolant through them. It would probably have to be a high boiling point liquid to keep it from expanding and cracking the chip from the internal pressure.

That would work but as pointed out earlier, nobody has an application where this is economical to bother with.

[CatalinaWOW]

It has been done, since the 1980's at least, for specialty applications.  None of the ones I have seen was for high volume products.  The most common use I am aware of is for readouts for focal plane arrays.

Lots of reasons why it is rare. 

Number 1 reason was Moore's law.  If you stack two chips on top of each other you double the density.  By the time the bugs were worked out in stacking those two chips density had increased until a single chip could handle the problem.

Heat as several mentioned is a problem.

Interconnects are huge issue.  Except for a few special cases like memory where interconnect is a limited number of buses the interconnect is tough.  Tough to design.  Tough to implement since the connections aren't repairable.  Getting a few thousand or a few tens of thousands of connects with no shorts and no opens is a big deal.

Which comes back to reason one.  When you have solved the interconnect and alignment problems for one generation, Moore's Law has delivered another generation to you, roughly four times harder than the last.

As Moore's Law starts to slow down some of these problems become more workable (or at least there is a better chance of a payoff for solving them) so we might start to see more 3D packages.

[Kilrah]

Imagine them making big solid copper or silicon traces in a grid pattern across the die and running coolant through them. It would probably have to be a high boiling point liquid to keep it from expanding and cracking the chip from the internal pressure.

Silicon is expensive, makes no sense at all to waste a lot of it just to contain coolant.
And as already mentioned, the heat pipes needed to carry the heat of a chip away already need to be much bigger than the chip itself, so it doesn't even work out.

[Marco]

The microbumps to connect  dies are comparatively huge, so you could in theory have relatively cheap interposers between the dies with cooling channels. Vastly cheaper than the main silicon.

[GeorgeOfTheJungle]

Inter-die inter-connects are a bitch... Just ask nVIDIA.

[Gyro]

^ Ask nVIDIA's customers, more like. 

[mikerj]

Some of Analog Devices "MicroConverter" micros with precision analog stack a digital die on top an an analog die.  The two dies use different semiconductor process, so can't be integrated on one die.

[coppercone2]

trenchfet