what if you use LVDT or something for sensing ?
Haven't seen those being used in CNC machines.
Quite a few modern microcontrollers - most notably a few new PICs and the Cypress PSoC series - have some programmable logic to allow unusual port I/O that previously required some form of external logic. I see that as the start of microcontrollers gaining FPGA-like abilities.
In a nutshell, that is why Intel bought Altera.
What I would like to see is a low cost FPGA with a hard microcontroller inside - it seems like the only options currently available are to use an external microcontroller (more cost/space, limited I/O interconnectivity) or to inefficiently create a soft core in the FPGA and significantly increase the design size.
It's the "low-cost" criterion that is the problem. It might be that the packaging that melds the micro and the FPGA fabric is "expensive," so it's warranted only on the high-end of things (think Zync). Bumping up a size of FPGA to accommodate a soft core might still have you in a chip that's less expensive than one with a hard core processor.
Make that low cost enough and it will be a real hit among advanced microcontroller developers. Now when they have to interface some weird device that's timing sensitive, rather than try to figure out how to (mis)use one of the peripherals to generate the waveforms or bit bang it in software while having to contend with making it work with the interrupts, they just program some logic to do exactly what they want.
I suppose the example here is Cypress PSoC, parts with which I admit that I have no experience.
I've done all of the possible combinations here: separate FPGA and processors talking to each other over some kind of standard bus. I've done PicoBlaze and MicroBlaze and even 8051 soft-cores embedded in the FPGA. I did a design with the Virtex-4 with the on-board PowerPC. I suppose at some point I'll do a Zync design. And I've done stuff which could well have been done in a microcontroller and just did it all in VHDL in the FPGA. What was chosen for each design depended on board space, relative complexity of each part of the design, and of course other external elements. What did the design actually need, what made the most sense? This is the part of engineering that's rarely talked about but is vital for a design to be successful.
Anyway, the FPGA vendors will decide what they will build based on what their biggest customers want, and we get to use whatever they end up making.
Microblaze core in MCU configuration takes about 2k LUT and 2k FFs (that's including interrupt controller through you can skip it if your project doesn't need it), so you can fit a couple of them even to the smallest Spartan-7. And in this configuration they easily reach 150 MHz clock speed even on a slowest speed grade.
2k LUTs is already a lot. If you don't need it fast, and if you have some BRAM to spare, the second winner for the RISC-V contest
managed to implement it with only 165 LUT, and he is still optimizing it. This might even fit in one of the smaller MAX10 FPGA, and it is a full 32 bit core.
2k LUTs is already a lot. If you don't need it fast, and if you have some BRAM to spare, the second winner for the RISC-V contest managed to implement it with only 165 LUT{/url], and he is still optimizing it. This might even fit in one of the smaller MAX10 FPGA, and it is a full 32 bit core.
2k LUT is nothing. I don't even look at FPGA that have less than 10k LUTs as they are useless for my purposes. Especially since Xilinx provides a complete set of peripheral IPs so you can literally build an entire system without writing a single like of HDL code, and - more importantly - they also provide a complete software toolchain with all drivers and libraries needed.
I'm also working on my very own RV64 core for fun, but I doubt it would even be as useful and have as complete infrastructure as one that comes for free for Microblaze.
There is also this one (picorv32) that has been tested on multiple vendor's platforms. It has also been used on an ASIC
https://content.riscv.org/wp-content/uploads/2017/12/Wed-1142-RISCV-Tim-Edwards.pdfhttps://github.com/cliffordwolf/picorv32As for lower-cost, I'm finding an stm32h7 + 8K-LUT Lattice part to be quite a powerful combination. Lower cost (relative to Zynq), no DDR memory routing, possible to do 4 layers if not all pins are needed, stm32h7 400MHz core appears to be comparable to a single core of the low-end Zynq for DSP application. In my opinion, this is pretty close to solving that middle area that has been missing.
2k LUTs is already a lot. If you don't need it fast, and if you have some BRAM to spare, the second winner for the RISC-V contest managed to implement it with only 165 LUT{/url], and he is still optimizing it. This might even fit in one of the smaller MAX10 FPGA, and it is a full 32 bit core.
I'ts a trick, but yes it is possible to run full RV32I complicant RISC-V in any FPGA/CPLD with 640 LUT or more. This includes almost all FPGA's ! Intel 10M02 is a bit hard target as it can not init RAM's but also still doable. 165 Xilinx LUT is pipelined 8 bit microengine based implementation without optimizations. Rewritten from scratch non-pipelined version is going to be less 70 LUT - for full SoC running multithreading Zephyr RTOS at about 1 Dhrystone MIPS.
Correction to Microblaze metrics: Microblaze MCS takes 644 LUT.
Correction to Microblaze metrics: Microblaze MCS takes 644 LUT.
I was talking about "full" Microblaze (not MCS) with GPIO and Interrupt controller modules as bare core isn't all that useful in practical situations.
Correction to Microblaze metrics: Microblaze MCS takes 644 LUT.
I was talking about "full" Microblaze (not MCS) with GPIO and Interrupt controller modules as bare core isn't all that useful in practical situations.
I know
full microblaze can also be below 2000, I just did give 644 as the "bottom" line metrics.
There's that old saw that goes, "If the young hobbyist learns Brand [$BRAND]'s devices and software, when s/he gets on the job s/he can push the organization towards that brand's parts." And that's bullshit. Any company that already does FPGAs already has a preferred vendor which won't change unless there's a Damn Good Reason to do so.
And all of those companies are of course many decades old and FPGA choice was made by godly existence and not real people... Did you hear about such thing as startup? Many of those made well established players bite the dust.
And how many startups actually use FPGAs and manage to survive long enough for the product to see the market? FPGA is a very expensive solution for niche needs, you won't find it in cheap consumer gear, for example.
I think the only recent exceptions that I am aware of are the OSVR HDK 1.0 head mounted display kit (in HDK 2.0 they have removed the FPGA as part of cost cutting because nothing used it even in the 1.0 version) and the project is dead (AFAIK) today. Its former CEO is now head of marketing for that laser phone charger thingamajig that Dave made a video on. One other consumer product that uses an FPGA (Lattice Ice40 I believe) is the HTC Vive and its controllers - as part of the Lighthouse tracking system where the thing is used to measure pulse time from the 30-something photodiodes. But that's gear that costs $500+.
Chronos camera, uh, huh? I think he uses Lattice part in there.
There's that old saw that goes, "If the young hobbyist learns Brand [$BRAND]'s devices and software, when s/he gets on the job s/he can push the organization towards that brand's parts." And that's bullshit. Any company that already does FPGAs already has a preferred vendor which won't change unless there's a Damn Good Reason to do so.
And all of those companies are of course many decades old and FPGA choice was made by godly existence and not real people... Did you hear about such thing as startup? Many of those made well established players bite the dust.
And how many startups actually use FPGAs and manage to survive long enough for the product to see the market? FPGA is a very expensive solution for niche needs, you won't find it in cheap consumer gear, for example.
I think the only recent exceptions that I am aware of are the OSVR HDK 1.0 head mounted display kit (in HDK 2.0 they have removed the FPGA as part of cost cutting because nothing used it even in the 1.0 version) and the project is dead (AFAIK) today. Its former CEO is now head of marketing for that laser phone charger thingamajig that Dave made a video on. One other consumer product that uses an FPGA (Lattice Ice40 I believe) is the HTC Vive and its controllers - as part of the Lighthouse tracking system where the thing is used to measure pulse time from the 30-something photodiodes. But that's gear that costs $500+.
Chronos camera, uh, huh? I think he uses Lattice part in there.
Chronos is hardly consumer gear.
Microblaze core in MCU configuration takes about 2k LUT and 2k FFs (that's including interrupt controller through you can skip it if your project doesn't need it), so you can fit a couple of them even to the smallest Spartan-7. And in this configuration they easily reach 150 MHz clock speed even on a slowest speed grade.
2k LUTs is already a lot. If you don't need it fast, and if you have some BRAM to spare, the second winner for the RISC-V contest managed to implement it with only 165 LUT, and he is still optimizing it. This might even fit in one of the smaller MAX10 FPGA, and it is a full 32 bit core.
Quite amazing you can fit anything useful (a 32bit core) in 165 LUTs. I could fit just a stupid UART transmitter with a LED display controller in that amount. But let me tell you - I am not a big friend with VHDL... yet.
If you want this sort of thing to stop, the trick isn't go after Xilinx, it's go after the lawyers that put their name to the letter. Report them to the bar association for legal harassment, for what is clearly fair-use. Next time Xilinx go to do it, their lawyers will stop them, rather than just blindly sending out letter.
I'm on Mr. Feranec's side on this one. He is demonstrating their product to help folks use it and of course he is showing the product that has the logo, etc. If this is a violation o copyright than any review video or educational video about a particular product is. They should be glad for the free publicity and advertisement for their product. So next time he'll use a competitor's product and when the folks who learn from his video need to use something in a real project they'll choose the competitor's project. This is why anyone and download and play with Oracle free....they want DBA's and developers to get to know their product so when it's time to buy something for production use they buy Oracle.
I'm on Mr. Feranec's side on this one. He is demonstrating their product to help folks use it and of course he is showing the product that has the logo, etc. If this is a violation o copyright than any review video or educational video about a particular product is. They should be glad for the free publicity and advertisement for their product. So next time he'll use a competitor's product and when the folks who learn from his video need to use something in a real project they'll choose the competitor's project. This is why anyone and download and play with Oracle free....they want DBA's and developers to get to know their product so when it's time to buy something for production use they buy Oracle.
did you miss the reply from Xilinx posted by both Mike and Dave on the previous page?
BTW, where are the Xilinx FPGA lessons in question, that has angered the Xilinx lawyers? I've just done a quick googling and could not find them. Maybe a wrong buzzword? Or have they been removed?