boost converter PCB layout

[andyturk]

I'm playing around with various DC/DC boost converters and most of them are very sensitive to board layout. The application notes all have recommended layouts that use large copper areas to minimize losses in the most sensitive parts of the circuit. Here's a typical example:



Note all the polygonal areas. How does one go about creating a layout like that? I'm comfortable with running "wires" from pin to pin, but I'm curious to know if there's a general way to expand thin traces into polygons that essentially tile the board. My current attempts (using Eagle Light) generate DRC errors when I draw polygons that overlap pads and wires. Is there some trick to getting these designs to pass DRC?

[OndraSter]

Make them properly in Eagle.

a) end them just where they should end and keep some space between this polygon and the other one
b) set their rank to higher to bring them to the front

[madires]

Name the polygons (same name as the net).

[poorchava]

In Diptrace you can specify network connections and pouring priority. This way you can control how the polygons share the space available.

[free_electron]

How does one go about creating a layout like that? I'm comfortable with running "wires" from pin to pin, but I'm curious to know if there's a general way to expand thin traces into polygons that essentially tile the board. My current attempts (using Eagle Light)

step 1 : take computer where eagle is installed , and all media carrying the eagle install files , pile on a heap , douse in gasoline and set ablaze.
step 2 : buy new computer and a REAL pcb layout tool ( Cadence . Mentor , Zuken , Altium )
step 3 : follow traingin course in PCB layout
step 4 : do a few hundred boards over a couple of decades

step 5 : now yuo will know how to do it.

there is a reason a pcb-design is called art-work ....

the way you do this knd of layout is you make a 'channel' for the high current pathways . you draw these as polygons connected to the net. and then you simply 'carve' into the polygons for the other tracks. the pcb tool will re-pour the polygons.

[jakeypoo]

Eagle is fine for this sort of thing.

Usually, what I will do is route out the traces as usual. Plan ahead for where you will place the polygons, fan out your traces to maximize size of critical signals.
Then layout your areas using the polygon tool, name your polygons the same as  the signals. Your polygons can overlap, use the rank property to determine which polygons take precedence over the others. This way, you can easily change sizes of polygons without having to retrace each neighbouring polygon.

Pay more attention to current carrying signals. Try to pay attention to how current will flow. The feedback pins, and logic pins can always just be routed with traces.

[andyturk]

How does one go about creating a layout like that? I'm comfortable with running "wires" from pin to pin, but I'm curious to know if there's a general way to expand thin traces into polygons that essentially tile the board. My current attempts (using Eagle Light)

step 1 : take computer where eagle is installed , and all media carrying the eagle install files , pile on a heap , douse in gasoline and set ablaze.
step 2 : buy new computer and a REAL pcb layout tool ( Cadence . Mentor , Zuken , Altium )
step 3 : follow traingin course in PCB layout
step 4 : do a few hundred boards over a couple of decades

step 5 : now yuo will know how to do it.

there is a reason a pcb-design is called art-work ....

the way you do this knd of layout is you make a 'channel' for the high current pathways . you draw these as polygons connected to the net. and then you simply 'carve' into the polygons for the other tracks. the pcb tool will re-pour the polygons.

LOL. How about I drive over to your place and use your copy of Altium?

Naming the polygons with signal names is what did the trick, even in Eagle. I drew all the polygons explicitly, but next time I'll try the channel idea. That way, the CAD tool can generate the gaps between the polygons instead of me lining them up by hand. I think this one is good enough for a run of $5 OSH Park boards though.

It uses the LTC3535 dual output boost converter to generate 3.3V and 5.0V from 2 alkaline cells. LTSpice says the 5.0V will have less than 1mV of ripple, which hopefully will make a nice clean analog supply. I'm curious to see how close to the simulation I can get.

[free_electron]

that's some dams small openings you have there between those polygons.... gonna be a trmendously expensive board to have made.... what is that less than 2 mils ?

[andyturk]

that's some dams small openings you have there between those polygons.... gonna be a trmendously expensive board to have made.... what is that less than 2 mils ?

Well, it passed the design rule check, but you're right, the gaps are a little small. I just looked through the DRC settings now, and didn't see anything that obviously checks for polygon clearance. Maybe Eagle doesn't check that?

There's no need to make the gaps that small, so I'll go back and make them larger. Good catch! Thanks.

[jakeypoo]

You can use the 'isolate' property of the polygon in eagle to set the spacing between polygons.
Set to 10-12mil and it will do the spacing for you.