How does my switching regulator layout look?

[plainsteve]

(I am a long-time DipTrace 2.x user who is trying out KiCad 9.)

I need to drop 5V down to 1v2 (and 3v3) to power an FPGA. Here is my KiCad9 layout for the RT8096B switching IC. I have never done this before... How does it look?

https://www.richtek.com/Products/Switching%20Regulators/DC_DC%20StepDown%20Convertor/RT8096B?sc_lang=en&specid=RT8096B

Four-layer board with stackup signal/power, GND, GND, signal/power. 1.2mm PCB thickness.

Thank you for any advice.

[asmi]

C1's ground connection is missing. Otherwise it's pretty good, but make sure you use 3D models to confirm DFM - some inductors are larger than their footprints, and yours is very close to the IC package.

[Kanta]

The layout is fine. It is necessary to determine the packaging of each component and ultimately convert it into a PDF file to view details.

[Doctorandus_P]

I would make a few changes.

Move R1 & R2 so the net to the feedback pin is as short as possible.
Rotate C1 clockwise so it's GND pad is closer to the center of U1 (Reduces loop area)
Add a GND via right in the center of U1 It shortens the current return path to C1.
R4 looks like an enable pin. It's position is not critical.
I'm not sure of the scale, but your clearance looks quite small. Normally clearances of pins of SMT IC's overlap. Overlapping clearances is perfectly normal. The constraint is that a clearance may not overlap with copper of another net.
Layer stackup with both internal layers as GND sounds good.
Reduce the loop area of the feedback. You do not want stray magnetic field of the inductor though this loop, as it introduces false voltage fluctuations in the feedback.
The inductor itself does not have to be very close to the IC, as current though the inductor changes relatively slowly.

Do a bit of research for an SMPS and do and use the magic words "hot loop" in your search. It gives some very good descriptions on exactly what to optimize for and why.

The goal of the courtyard (purple lines) is to reserve enough space around a footprint to allow for DFM. (But there are different "density classes". Normally the courtyards of the footprints can be snapped together and that should not give DFM problems. But you're always responsible for your own projects and verify whether everything works together for you. I usually print out the PCB on paper and glue it on cardboard and then physically test all "critical" areas with the real parts.

[plainsteve]

[ Specified attachment is not available ]Thank you. Made these changes:

• Moved C1 and connected it to ground. Moved R3.
• I moved R1 and R2 to make FB connection short.
• Tapered the copper polygon of the 1v2 output rail down from the inductor to the farther of the two output caps.
• Tightened polygons and ground via placements.

I might put the components closer, min. 0.5mm component spacing, as I intend to have this board assembled (I do not want to hand solder these!).

[multipla]

I would connect C1's ground pad also on the top layer directly to the IC ground, it makes the current loop area even smaller.
Also I'd rather keep the feedback signal on the top layer as well and instead use vias to connect the enable signal to the IC. Move the feedback resistors also as close to the IC as possible, the feedback net is sensitive to noise after the first resistor. You can move the enable resistor a bit further away, the feedback parts have priority.

[Doctorandus_P]

Move the feedback resistors also as close to the IC as possible, the feedback net is sensitive to noise after the first resistor.

Yes, I also already mentioned that. And then he moved it only half way.
Goal is:
1. Put R1 where R4 is now.
2. Put R2 south of R3 or R2.
3. Put R4 elsewhere. It's location is not critical.

Doing this makes the path from the +1V2 net of R1 longer. That is not important by itself, but the enclosed loop area is important, and should be minimized.

1. Rotate C2 and C3 clockwise 90 degrees.
2. Put the GND pads closer to pin 2.
3. This reduces the loop area.

It may be better (I'm not sure here) to:
1. Rotate C2 and C3 anti clockwise.
2. Rely only on the GND plane for connection (with plenty of via's).
3. Route the +1V2 in between U1 and the output capacitors to R1.

[multipla]

[..]
1. Rotate C2 and C3 clockwise 90 degrees.
2. Put the GND pads closer to pin 2.
3. This reduces the loop area.
[..]

I agree.
Also possible would be adding a 0402 MLCC just east of the IC, connecting GND directly to the pad and 1V2 directly to the inductor's pad above of it. C2 and C3 could then stay where they are at the moment. This leaves the feedback trace with quite some loop area though, but I think in the end this wouldn't make much difference anyway.
But R1 and R2 should be mover together towards the left, until their pads are under the IC pad 6, and place R4 elsewhere in the vicinity, as you wrote

[plainsteve]

Thank you all for your comments. Here is my latest attempt. Note that via-in-pad is not available to me. It seems too expensive. (I am using PCBWay for PCB fab and assembly, qty up to 1000. Maybe I need to look at the costs again.)

Criticisms welcome.

[Doctorandus_P]

You can put R4 father away, that's OK, but the blue track cutting the GND plane in sections betwen the IC and the output capacitors is not good. And in general, you should never ever make such cuts though a GND plane. For an SMPS, you do not want to put anything in the "input loop" and the "output loop". If you can route a track in between the pads of R1, then you can put R4 under R1 and keep the GND plane intact.

I would also put the via in the GND net of R2 in between the resistor and the IC to make this loop shorter. If that does not fit, then you can use two via's close to each other to have tracks cross each other on the PCB, but try to keep such interruptions in the GND plane below 5mm or so.

For the rest, it looks good, not much more left that can be optimized.

[plainsteve]

The PCB stack-up is signal/power, ground, ground, signal/power. The blue trace is on layer 4, so neither of the inner ground planes are cut. Am I misunderstanding?

I think I can swing R2's ground via 90 degrees clockwise so it's to the north of R2. Should I use a second via anyway?

Almost there?! Sweet. Then I can replicate this layout for the 3v3 rail.

[Doctorandus_P]

Oopsie.

I lost some context from seeing too many different threads. As long as you have GND layers on the inner layers, then a track on the back does in deed not matter at alll.

If you need to shift R2 a bit downward to make room for the via in between it and the IC, then that's all right. It's not the absolute position that counts, but the loop area, which introduces paracitic inductance. And adding a 2nd or even a 3rd via next to the pad to the GND plane never hurts.

Some people clam that vias have a high (self) inductance, but I'm not so convinced that self inductance of a via is much bigger then of a straight piece of track.

[plainsteve]

I moved the via north of R2 and added another via to cut that malicious via inductance in half.

Thanks again to all! 

[Doctorandus_P]

Probably plenty good.

If anything to remark is left, then it's that you probably spent way to much time on this in total. But it's also part of the learning experience.

And overall, it would be quite interesting to make a bunch of "deliberate faults", and then send them all to the PCB fab and measure how big the faults really influence ripple noise and EMC stuff.

[multipla]

[..]
If anything to remark is left, [..]

I actually even have one more remark, which is irrelevant in this case, but a good thing to look out for: When one switches a signal's layer from Top to Bottom, one should also place a ground via right next to the signal via, so the return current can also change from layer 2 to layer three, which keeps the loop inductance as low as possible.
Here it's only a static enable signal, so of course it's irrelevant, but for stuff like PWM signals or communication lines, if vias can't be avoided at all, return vias should also be added. It's for example in Ott's EMC book chapter 16.3.3, which I find gives a good explanation and it just feels right as well.

[Doctorandus_P]

I agree on both occasions (Yes, it's a real thing, Yes, it's not applicable here). Robert Feranec has also made a few quite good video's on this topic. And with FEM simulations of how return currents behave. The transition frequency where the impedance changes from the shortest DC path to hugging the "forward" current is surprisingly low. It's around a few kHz.