Options for via-in-pad on high current fets (for thermal control)

[Psi]

For PCBs, what are the via-in-pad options for putting thermal via's in the middle of a D2PAK to get better thermal management? Obviously something is needed to avoid losing solder down the holes.

I know you can epoxy fill vias and plate over them, but afaik this is only for small via's and not the size you use for thermal management.

Does anyone know what options exist and what is the cheapest?
Is it best to put no holes in the pad and instead put them around the outside?

I need to pass around 40A through 1mR mosfet and it will probably be 2oz copper.
So 2W or so. However there will be lots of other mosfets on the same PCB
so i really want to pull the heat out of the mosfets into the middle pcb layers as much as humanly possible.

Previous threads
https://www.eevblog.com/forum/projects/question-about-min-vds-for-12v-dc-motor-load-switching-(no-pwm)/msg3473254/#msg3473254
https://www.eevblog.com/forum/projects/questions-on-designing-fwdrev-12v-dc-motor-controller-for-80a-typ-(200a-peak)/msg3379404/#msg3379404

[T3sl4co1l]

You can fill any via, the more important part is it's a laborious step so it's expensive and best avoided.

Use small vias, less prone to wicking solder (<= 0.3mm i.d.).  Plan for extra solder paste, and calculate how much would be left assuming all the vias fill up -- leave enough to give a small fillet on the tab.  The rest, fill in around with vias.  Do not tent the vias, leave them open both sides.

One or two watts is no problem for vias around the periphery.  More concerning is, if you have "lots" of FETs, you'll need to get a lot of heat out, period.  Consider clamping PCB to heatsink with thermal pad?

Tim

[Psi]

More concerning is, if you have "lots" of FETs, you'll need to get a lot of heat out, period.  Consider clamping PCB to heatsink with thermal pad?

Thanks.

Yes, the entire bottom of the PCB (130x120mm) will be attached to an aluminum plate with thermal adhesive tape.
The mosfets are all on the top layer so the critical thing is to get the heat out of the tiny mosfet package and spread it out over the PCB so the metal plate can do its thing.

Currently have ~16x 0.3mm via's for each mosfet's connection around the outside (none in pad)
PCB is 6 layer. The plan is 2oz outer layers and 4oz inner layers, but this will depend on pricing from pcb fab.
(Soldermask not shown in pic to make vias viewable)

[T3sl4co1l]

Ah yeah, your high current motor driver thingy?

FYI to readers: if you're making another thread in a series, it helps to refer to your earlier threads for context, so we don't have to ask for clarification.  We don't all read every thread, or remember who all has posted them.  (Which, for my part, I'm poor at names... clearly I don't have much of an excuse in the other matter... )

Huh whats the device in the middle, it's not a MOSFET, all four pins are common.  Diode?  TVS?  Not aware of what's in PDSO-8, or LFPAK or whatever this is, that's a diode...

Can save a good, some mm's between the FETs and terminal blocks?

4oz inner is probably not the greatest.  You'll have to spend more clearance, including around vias -- may end up reducing cross section in critical areas.  The vias can be spread out to somewhat lower density to help with this.  Heat and current spreading on the top layers is paramount, and you may find 3oz is okay on that as well as meeting tolerances.  (You'll probably need to avoid TSSOP and such, but SOIC is fine.)

No bypass caps?  Or, everything on the bottom side?  I don't see gate resistors either... note by the way each transistor needs its own gate resistor, they can't be wired hard in parallel.

I don't like the supply TVSs being all the way off to the side(s), especially if there's no supply bypass.  That's a good... 100nH maybe?  Don't have a good feel for scale here, guessing that's like a 10cm wide loop?  The left and right legs might be okay but the middle one is maybe at risk here...

Tim

[Psi]

I have added in the 2 previous threads to the main post.

Yes its a diode, each block is made of 6 mosfets in parallel plus 1 diode. (3 mosfets on each side)
diode will probably be something like STPS3045DJFY-TR.

[Psi]

No bypass caps?  Or, everything on the bottom side?  I don't see gate resistors either... note by the way each transistor needs its own gate resistor, they can't be wired hard in parallel.

Adding gate resistors atm, yeah, forgot them.

There's a 1000uF electrolytic and TVS diode at each end across the main supply rail.
Will try to add one in the middle as well.

Do they have to be very large value caps like 1000uF?
I have room to pepper some 10uF ceramics around the supply rails, but large electrolytics are problematic.

[T3sl4co1l]

Hmm, do you know you need that schottky?  It's slightly lower voltage drop than the body diode(s), but it's also just one, there's no heat spreading... not that there's going to be perfect current sharing between body diodes either, but I wouldn't expect to rely on either for most operation.  Surely this will be driven full-wave, sync rect is for free?

TVSs in those locations would be a good alternative to TVSs between rails, that's why I asked diode or TVS...

Note that, aside from if you're strapped for space overall, the individual legs don't need to be crammed together, they can be spaced out quite a bit.  Limited only by lateral current capacity, and you could surface-mount some bus bar onto the board, or use more terminals and screw some down, etc.  The layout could alternate TVS/leg/TVS all the way across (one TVS will serve for two legs).

1000uF, sounds very, very small... I would think more like 10 of those per position, if you're going for bypassing, and of the lowest ESR you can find.  Maybe less if polymer (but that'll get pretty expensive?)  (In which case, TVSs shouldn't be necessary, unless you have an overvoltage condition to also protect against, say under load dump or regenerative braking.)

I would want to know more about the power source, and wiring, to make a decision there.  Also, this was only supposed to be slow switching, not PWM, right?  You still need to prepare for switching, at least once, at all; doing it repetitively is just a matter of losses, which is all that can be saved in that case.

Tim

[Psi]

No overvoltage condition expected or load dump or regenerative braking.
Just the kickback from the DC motor at turn off.

Keep in mind this thing is only on/off with human use of the device. No switching other than user control input.
It will have at absolute minimum 1 second between state changes to recover which I can enforce in software.
The diode/TVS can handle a fair bit of energy since it has plenty of cool down time.

Hm.. If many 1000uf caps are required for solving the issue using caps then I should probably lose them and simply focus on a TVS-only solution.

As you said, put TVS in a row in between the mosfets in a repeating pattern.
I do suspect that the 5kW TVS I have is perhaps overkill. I maybe able to use many smaller TVS diodes instead of a few big ones.

[T3sl4co1l]

Why the three phases, is this not a motor thing?  I remember something like that, but maybe I'm conflating it with another thread that was running at the time...

If it's infrequent, yeah, I'd be fine with a TVS (given worst-case source and load currents and inductances, can calculate how big is actually needed) in place of those schottkys in the half bridges, and nothing directly between supplies, maybe just a few 100 uF total of ceramic bypasses to handle the highest frequencies.

Tim

[Psi]

Yes, two winch motors but only one needs to be on at a time.
There 3x half-bridges. One common to both motors.
So either motor can have full H-bridge control

For that PCB design above only 6 top and 6 bottom fets will be active at any time.
It's around 12W max (6W top, 6W bottom, spread across the 12 active fets).
Plus a little bit of heat loss in the copper.

[Psi]

This project has been through a few revisions and I have design that can do 150A for the time required and only gets to 40C from ambient 18C.  And most importantly has never blown up during testing.

My question is, Is this number of via's excessive?

It looks excessive to me, but thought id ask someone with more experience with high current PCBs.
Does 2k holes on a 130x125 PCB sound excessive.

PCB is 6 layer 3oz (all layers)
holes are 0.3mm
PCB size is 130x125mm (5x5inches)
Total holes (all sizes) 1853
Each FET gets around 25A but only 12 of them are on at any one time. (Two H bridges sharing one half bridge and only one H bridge is used at once)

[T3sl4co1l]

Probably.

You can calculate the trade-off as, say, the ratio of annular resistance to total via resistance.

So, take the wall thickness (1-2oz?), circumference of the hole (exactly: mean circumference of the via 'barrel'), number of vias, and resistivity of plated copper.  Compare that to the annulus of copper around a via, to its surroundings -- roughly speaking, this should be the distance to neighboring vias, or to pads, etc.  You can model it a few ways, or even cook up a full 3D model and uh... does FEMM do electric fields, or, is there a different simulator to do that?

What the distance to neighboring vias tells you is, how much resistance you save from a given pattern density of vias. Or, at what point it's not worth adding more vias because the two layers are already fully connected.  That is, if current flow on the top layer shall be diverted to another layer, how many vias, or rows thereof, are needed to ensure full sharing?  So, maybe consider alternative patterns or adjust density as needed there.

What the distance to neighboring pads tells you is, total resistance.  So, power dissipation and temp rise.  As for temp rise, you need thermal resistance to sinks also.  (Was this packed under thermal pads, or open air, or what?)

2k holes does sound excessive.  But maybe it's justified, I don't know.  Run the numbers, compare via resistance to pour resistance and see!

Tim

[Berni]

That amount of vias don't look too excessive to me, its about what i usually do when i want to run high currents or move a lot of heat.

As for vias under D2PAK MOSFETs, it's perfectly fine to do, i do it all the time. The trick is to use tented vias (meaning they are covered by soldermask). The solder mask covers the hole, but more importantly it does not leave any exposed copper on the underside of the board. The via hole doesn't actually suck up that much solder, especially once the soldermask climbs down into the via and gunks up the walls. The big problem is when you have exposed copper on the underside, since then the solder will climb trough the via and collect on the bottom of the board, this is what causes soldering problems because it can pull away a lot of solder.

If you do find a issue with too much solder collecting inside the via you can simply apply more. Normally the D2PAK footprints have a paste mask made of smaller squares to reduce the amount of paste (it can otherwise get lifted by too much solder) so you can just increase the size of those squares to get more solder to compensate

[T3sl4co1l]

Note that the vias must be tented BOTH SIDES, otherwise trapped gas will bubble up and leave voids in the solder joint.

Tenting will not reliably plug vias.  Small vias moreso than larger ones.  If you need plugged or capped vias, you'll need to pay for such -- it's available, but not cheap.

Solder filled vias aren't too bad (gives a mild improvement in electrical/thermal), and may do so reliably on wave soldering (reflow obviously is limited by pasting).  You can calculate the excess volume of solder for a given paste pattern, and place as many vias as will fill by the same.

Which, hopefully they fill, if you're planning to; modest sized vias are best (~0.5mm i.d.), as very thin vias (0.2-0.3mm) tend to wick solder poorly.  Lead-free also wicks slower than leaded, YMMV.

Tim

[Berni]

I don't tent both sides of a via.

Just tenting the bottom works fine enough. The via itself can't really contain a whole lot of solder (Its the ball of solder that forms on the bottom that can) while some of the soldermask gets wicked into the via somewhat, covering the walls and preventing it from wicking solder all the way to the bottom. Additionally when the paste gets applied to the pad some solder paste is pushed down into the via to fill it up already.

It's not really a some rigorous formally approved way of doing it, but it appears to work very well in practice. Unless you are doing some massive 10k+ qty production runs i wouldn't be worried about it.

[nctnico]

I have been using untented / open vias for QFN and other power-pad packages for years and never had soldering issues with them (probably over 20k units in total with various designs done by various manufacturers). Actually I like having vias in power pads because it makes the amount of paste under the package less critical. Whenever it is too much, it will get sucked into the vias. Vice versa it allows to solder the power pad from the bottom of the PCB using hot air for a manually assembled prototype.

[T3sl4co1l]

Oh, that might be unclear -- if tenting, tent both sides, otherwise tent none and expect some solder fill.

Tim

[cjurczak]

Not sure if you've resolved your problem, but I recently had to deal with this recently on a design.  We found several solutions, but finally designed on a VIPPO in the end. 

We considered/tried pasting both sides of thermal pad to get more solder to the situation. 
We considered/tried a step stencil to again apply more solder to the board.
We considered a using a solder preform, another way to bring more solder to the party.
We considered more smaller vias that were less likely to wick away solder.
We considered/tried additional plating to fill vias with copper. 

In my circumstance the best thermal performance was additional copper in the vias, but this board was Hoz copper, and we couldn't tolerate the additional surface copper.  Additional paste helped a lot, but in the end it was inconsistent.  VIPPO eliminated the problem, and didn't effect the budget on that PCB much (8 layer, several 1000/yr).

[Pseudobyte]

If you can afford it, I would advocate for a small drill via (12mil) and specify that drill size to be plated shut. Plating shut is far superior to any plugging process (10x better heat transfer). It is the best case scenario for current/heat transfer unless you compare it to copper inlay. Large amounts of vias actually inhibit the heat flux through the dielectric, which is the primary way heat spreads through a circuit board. Standard vias in pads only provide a marginal decrease in component temperature compared to just having a large plane on the opposing side of the board. The more copper you can keep on the board the cheaper it is to manufacture, and the better thermal performance you will have. You paid for the copper, you might as well keep as much of it as possible.