PCBWay issue with QFN solder bridge, what to do?

[VEGETA]

I always tent unless:
- want the ability to hand solder the QFN, by putting solder on top side, then put chip, then heating from bottom side with iron (time intensive)
- want extra thermal capability by adding solder to the vias (probably not a huge difference)

I wouldn't bother with filling, and you don't need to ask, the quote page gives ~$120 more for 2 layer plugged vias.

by tenting you mean cover them with solder mask? this won't be good here since they are vias in a pad situation. I need the good contact between the pad of the IC and the smt pad (with its vias).

is there a solution to fill but to keep the surface of the via copper exposed and flat? so that it gets soldered nicely and give good conductance? please check the image of the pad above.

the entire quote for assembly + board + component is about 107$. will filling add an extra 120$ for it??

Also, can not filling really make performance worse? or degrade soldering quality of the pad? I gave them instruction to put more solder paste and make sure soldering is good.

[thm_w]

Tenting only on the non-component side, as wraper explained.
You can use their quote page, it adds $120: https://www.pcbway.com/orderonline.aspx

[VEGETA]

they mentioned that the vias will plated. does this mean copper? and that would make good connection to IC thermal pad?

I mean should I use the filling or just go without it? having good connection is important since this is a dual buck converter which will supply 3 amps and 0.5 amps continuously. It has the thermal pad as ground and it is the only direct connection to bottom layer ground plain.

[SiliconWizard]

What's the pitch of this QFN? (Sorry if I missed it.)

Only high-spec (and pricy) fabs manage to put soldermask between pads of fine-pitch parts, and that's usually pretty expensive.
IME, no soldermask between pads is not a problem (as long as the assembly fab is not a dead cow) for pitches > 0.5mm. It can get tricky for <= 0.5mm. 0.4mm being usually the spot where things get really problematic and start requiring manual touch-ups.

[julian1]

Is this for a prototype that is hand soldered? Or a production run with many boards? For a prototype you can solder the qfn, and then desolder it to inspect and verify adequate solder coverage of the gnd pad.   

For reference, I use 4 or 5 vias for small qfn, and never had a problem.

If the via coverage area to pad surface area ratio is high (eg. maybe 50%) then I believe tenting becomes more important (eg. via-in-pad for fpga, or high-density vias for heatsinking), to prevent the vias sucking solder away from the joint. 

In the worst case and for a prototype, you can probably just smear wet epoxy to the back-side, and plug the vias yourself.

[VEGETA]

What's the pitch of this QFN? (Sorry if I missed it.)

Only high-spec (and pricy) fabs manage to put soldermask between pads of fine-pitch parts, and that's usually pretty expensive.
IME, no soldermask between pads is not a problem (as long as the assembly fab is not a dead cow) for pitches > 0.5mm. It can get tricky for <= 0.5mm. 0.4mm being usually the spot where things get really problematic and start requiring manual touch-ups.

soldermask bridge issue has been solved now, the used footprint was wrong despite being from TI.

right now the biggest issue is to fill the vias or not.

please see images above about the footprint with the thermal vias. all of those 9 vias couples the ic to bottom ground plain... top ground plain cannot reach the ic.

Is this for a prototype that is hand soldered?

this is a prototype but will be fully assembled by factory. it is expected to work, so will be the production design.

it is a via-in-pad situation, and i require good solder connection to the ic thermal pad which is also GND.

can the remaining space really take care of it if i tented or filled them?

the manufacturer tells me they will be filled with risen and plated. plated means copper = good connection. but later on she tells me it won't be conductive surface so go figure.

the thermal pad (GND) area is 2.7x2.7cm, and it has 9 vias (0.3mm hole, 0.6mm pad)

[julian1]

If you are price sensitive, then forgo the tenting process. Desolder the part when you receive the prototype, and validate. If you are not-price sensitive, then manufacture it both ways and evaluate.

the thermal pad (GND) area is 2.7x2.7cm, and it has 9 vias (0.3mm hole, 0.6mm pad)

I don't see a small number of vias like that, sucking much solder out of the joint and causing a problem. However there may be an issue that for higher thermal and current handling you ideally want more vias. Does the part datasheet provide guidance?

[wraper]

I don't see a small number of vias like that, sucking much solder out of the joint and causing a problem.

For such a small chip even single via can suck all of the solder if there is enough of exposed copper on the other side to receive all of it.

[julian1]

Dave's video, might help give you a sense of how vias can suck the solder away from the joint. In this case lots of vias used under a power mosfet for power/heat dissipation.


https://youtu.be/pKX50E_14MQ?t=2775

[wraper]

This video, might help give you a sense of how vias can suck the solder away from the joint. In this case lots of vias used under a power mosfet for power/heat dissipation.

https://youtu.be/pKX50E_14MQ?t=2775

For power MOSFETs like that (D2PAK, DPAK package) it's much less of a problem since soldering of the tab does not significantly affect soldering of the terminals. For QFN on other hand it's a very serious factor you need to consider, since it can completely screw soldering quality, cause solder bridging and other nasty things.

[VEGETA]

here is the attached image.  thermal pad is 2.7x2.7mm not cm, sorry for this!



9 vias like that was recommended by the official datasheet: https://www.ti.com/lit/ds/symlink/tps54394.pdf in page 26.

I also attached solder paste layer image, you can see some if it on top of some vias. my vias are larger than datasheet because <0.3mm will require expensive drill

[julian1]

Yes, I think defer to Wraper's experience to rule out issues around automated assembly. 

[VEGETA]

Yes, I think defer to Wraper's experience to rule out issues around automated assembly.

do what is the best solution here? redistribute vias to outside and leave the inside just the pad and then adjust the solder paste to not cover the vias??

removing the middle via maybe can do that? but even though, tent\fill or not?

[julian1]

No. Follow the datasheet, and fill the vias, to rule out issues.

I have got aways got away without filling for qfn, but I hand solder, and have lots of control over the amount of paste, can rework etc. That's a different scenario from manufacturing.

[VEGETA]

No. Follow the datasheet, and fill the vias, to rule out issues.

I have got aways got away without filling for qfn, but I hand solder, and have lots of control over the amount of paste, can rework etc. That's a different scenario from manufacturing.

well, in your experience, for my particular state and footprint... can filling them affect solder quality and thermal\electrical firmness between pad and ic? since this is all care about. I don't want the 9 vias to make the remaining area not suitable or so little touching to the IC and therefore no good electrical signal.

the other 2 ground pins have 1 via each and it won't be enough to put the current imo. but on the bright side, these 2 ground pins are firmly connected to the big ground pad which has the vias

[julian1]

  can filling them affect solder quality and thermal\electrical firmness between pad and ic? since this is all care about. I don't want the 9 vias to make the remaining area not suitable or so little touching to the IC and therefore no good electrical signal.

No, it's the other way around. Not filling them, risks the solder being pulled into the vias from capillary action, which creates a bad solder joint with poor electrical and thermal properties. 

[nctnico]

  can filling them affect solder quality and thermal\electrical firmness between pad and ic? since this is all care about. I don't want the 9 vias to make the remaining area not suitable or so little touching to the IC and therefore no good electrical signal.

No, it's the other way around. Not filling them, risks the solder being pulled into the vias from capillary action, which creates a bad solder joint with poor electrical and thermal properties.

Lead free solder is typically not prone to wicking away from under a chip when using small holes (like 0.4mm vias). Or put differently: I have had a lot (thousands) of boards produced with small vias under QFNs and I have yet to see a board where the solder has reached the other end of the board.

[VEGETA]

so my vias with hole of 0.3mm will never leak or have any risk of bad solder joint? well, the pcbway person was the one who raised the question to me, i never knew this much about vias being filled or so.

>> not filling them:

jullian, I think now I understand the risk of not filling them, but nctnico seems to have the opinion and testing experience that such 0.3mm vias will never pose such risks.

however, my question was about also the soldering and electrical\thermal performance of the IC thermal pad if I used the filling... and ofc because the filled vias will be covered and thus will be 9 circles of no soldering area. this is what concerns me.

my vias are 0.3mm hole and 0.6mm diameter, meaning about 0.15mm of via copper all around it... so, if they are filled with risen, will the via copper itself be covered as well?

if it will not be covered, then it will be no problem! since it will get connected to other pad area with solder... my concern if it will be covered, then we will have 9x0.6mm circles of "no solder" breaking the area which may hinder the performance.

what is your experience on this?

the pcbway representative does not answer questions in details.

[ataradov]

Nobody would be able to answer definitely if it will work fir you or not.  It all depends on the specifics of the assembly process, like temperature profile and solder paste used.

If you are making small runs, don't worry about it too much unless you actually see the issue, in which case you will have to make adjustments.

If you are making huge production runs, plug the holes, don't risk it. 

I definitely seen 0.3 mm holes wick the solder through during manual rework when there were no issues during the automated assembly. Obviously manual rework does not follow any standard temperature profiles and is likely huger temperature than a regular reflow process.

[VEGETA]

Nobody would be able to answer definitely if it will work fir you or not.  It all depends on the specifics of the assembly process, like temperature profile and solder paste used.

If you are making small runs, don't worry about it too much unless you actually see the issue, in which case you will have to make adjustments.

If you are making huge production runs, plug the holes, don't risk it.

well, for plugging the holes... my holes are 0.3mm and the entire via is 0.6mm, so the via copper is about 0.15mm all around. if they are risen filled (or any fill), will the filling and covering using non-conductive material be on just the 0.3mm or the non-conductive material will be the entire 0.6mm area?

if only the 0.3mm then yes, it will be no problem for any performance and so on.

how can we be sure? the pcbway rep says via surface will be plated but also non-conductive, she does not give much details.

[ataradov]

The entire via does not have to be 0.6 mm, it is all copper anyway, it can be anything. Plugged vias and vias just covered with solder mask are very different. Full plugging is generally more expensive. And for simply covered vias - pick a diameter that your board manufacturer can reliably produce. They will not be able to just cover 0.3 mm, since that't the hole. Solder mask needs something to hold on to.

You are overthinking this. Just make the board with holes open and see what happens.

[VEGETA]

The entire via does not have to be 0.6 mm, it is all copper anyway, it can be anything. Plugged vias and vias just covered with solder mask are very different. Full plugging is generally more expensive. And for simply covered vias - pick a diameter that your board manufacturer can reliably produce. They will not be able to just cover 0.3 mm, since that't the hole. Solder mask needs something to hold on to.

You are overthinking this. Just make the board with holes open and see what happens.

first my holes were 0.2mm and they charged me twice because of using a fancy drill, now changed it to 0.3mm.

assuming the vias covered with risen, it will be 9x0.6mm in that area. will the other remaining area be enough for the ic to have best performance? i mean those 9 filled and covered vias won't affect it/??

i worry because if proto board worked with no covering, then for some reason didn't work well for production... i will be losing a lot of money

[Bud]

vias will be covered and thus will be 9 circles of no soldering area. this is what concerns me.

my vias are 0.3mm hole and 0.6mm diameter, meaning about 0.15mm of via copper all around it... so, if they are filled with risen, will the via copper itself be covered as well?

Remove 4 corner vias and tent the remaining ones, problem solved.

[VEGETA]

vias will be covered and thus will be 9 circles of no soldering area. this is what concerns me.

my vias are 0.3mm hole and 0.6mm diameter, meaning about 0.15mm of via copper all around it... so, if they are filled with risen, will the via copper itself be covered as well?

Remove 4 corner vias and tent the remaining ones, problem solved.

aha so the remaining ones will be enough to properly couple the IC to the internal bottom layer ground plain and have good thermal performance... at say 4 amps total load?

[Bud]

If max current is a concern you can adjust the remaining via size to compensate for loss of removed vias stem surface area.