problem with lvs in cadence layout using calibre

[salar_1991]

hi i'm testing the layout for my circuit using cadence calibre tool that is a transimpedance amplifier and im using cadence 6.14. drc test is ok but i encountered some errors in lvs check . there is 16 errors including 1 port error which points to gnd and i couldn't fix it and i checked the layer of pin and lable problem is not from that . there are 4 incorrect instance errors that's pointing to 4 spiral inductor in the circuit and there are 11 net errors. can anyone help me ? thanks in advance .

[endevor100]

Typically in that situation I've found that you probably forgot to connect something. The DRC just looks to find basic problems that would cause issues (things too close together, traces from different nets that are connected, etc...). The LVS is what actually looks at you schematic and makes sure that you're faithfully recreated that in your layout. If you look at your Output button on the LVS window it will give you more detailed information on its analysis of your design. If there are no smoking guns there then I find it most useful to look at the extracted view where Cadence adds net numbers to all of the devices. If two points should be connected to the same net, but the net listed in the extracted view is different then you've found a problem and now you know at least the first thing to fix. I've seen plenty of occasions where 1 missing connection can cause dozens of LVS errors so don't get discouraged.