QFN32 footprint with thermal "vias"

[Skauber]

I'm working on a project where I need to control some LEDs for backlighting and indication on a keypad. I decided to use the LED driver IS31FL3239 in a QFN32 package. I downloaded the footprint and model from Lumissil, the manufacturer, but I wanted to modify the footprint with some thermal vias. The suggestion first was 0.2mm vias, but that would inflate the production cost a lot, from 10usd to 60usd, so I am limited to minimum 0.3mm drill holes. I edited the footprint myself based on some suggestions online in using normal through-hole pads with 0.3mm drill holes, and it was said in order to prevent the solder paste from running through the holes and cause a badly soldered center pad, I should divide the centerpad like a window. I find it a little counterintuitive, but I dont have experience with using these type of footprints. Is this footprint good to go, or should I have one single centerpad with the thermal holes just going through it? It is intended to be assembled at JLC, but I also want to make it easier on myself if I have to rework a chip here with my hot air station.

[tszaboo]

I'm working on a project where I need to control some LEDs for backlighting and indication on a keypad. I decided to use the LED driver IS31FL3239 in a QFN32 package. I downloaded the footprint and model from Lumissil, the manufacturer, but I wanted to modify the footprint with some thermal vias. The suggestion first was 0.2mm vias, but that would inflate the production cost a lot, from 10usd to 60usd, so I am limited to minimum 0.3mm drill holes. I edited the footprint myself based on some suggestions online in using normal through-hole pads with 0.3mm drill holes, and it was said in order to prevent the solder paste from running through the holes and cause a badly soldered center pad, I should divide the centerpad like a window. I find it a little counterintuitive, but I dont have experience with using these type of footprints. Is this footprint good to go, or should I have one single centerpad with the thermal holes just going through it? It is intended to be assembled at JLC, but I also want to make it easier on myself if I have to rework a chip here with my hot air station.

I wouldn't do that. Place 5 vias into the pad, and make the pad the same size as the thermal pad recommendation in the IC datasheet.
According to several IPC standards, the assembly house is responsible to make sure that their paste mask is the correct size adn shape.
And yes, 0.3mm vis will wick away some of the solder, but it's fine. Even if 50% of the center pad is covered in solder there is barely any effect on the heat. There are very good application notes from TI for this.

[Skauber]

Ok, thanks for the response. My gut feeling was that a normal pad as specified in the datasheet would be best, and not divided up into 4 zones. Will proceed with the footprint that the manufacturer provided, only with the 5 vias added for thermal and ground connection.

[Doctorandus_P]

Solder wicking is a real issue, especially with small pads, but on such big pads the problem is more the opposite. Without extra pecautions, there is far to much solder paste on the center pad, and this can result in the whole package floating on the solder blob and the QFN pads not being soldered at all.

I added a screenshot of one of the QFN-32 footprints from KiCad. (They come in different pitch sizes) The bright red is the copper, while the greyed out areas are the F.Paste layer (holes in the soldering stencil) So the copper is a big exposed pad and has the via's while the solder paste has 3 smaller pads. This deposits less solder on the big pad (to prevent floating), and the extra ridges also keep the squeegee at the correct height (with a big hole, the flexible squeegee dips into the hole and removes some (unknown amount) of solder paste.

Some of the solder wicking into the via's is (mostly?) a good thing for the center pad of a QFN. It gets rid of "excess" solder. And because the underside of an QFN is flat, it needs very little solder on the center pad. Because this solder layer is so thin it also has a higher capillary effect then the holes. So only the excess gets wicked into the holes.

The rounded corners on all solder stencil apertures are also a nice detail. This improved release of the solder paste when the mask is lifted. (No paste gets stuck in corners). This is also an IPC recommendation, and a DFM improvement.

KiCad's footprint is also not ideal. I have seen footprint designs where all the thermal vias are covered by the solder stencil. This prevents solder paste from being squeezed into the vias (which is a production variable) and thus the total amount of solder paste is better controlled.

I would also not rely too much on a footprint suggestion of some manufacturer. The paste machine, PnP, solder paste and soldering process used are all important production parameters, and these influence the optimal solder paste apertures.

[nctnico]

I would leave paste mask optimisations to the assembler. They know their process best and what works best.

[asmi]

I would just mention that the best way to deal with it is to use VIPPO, preferably with metal filling (EXPENSIVE), but any filling will do if you aren't trying to extract the maximum amount of heat - the cost be damned. They create flat surface with no holes, so no soldering problems whatsoever - beyond those typical for any QFNs.

[tszaboo]

I would just mention that the best way to deal with it is to use VIPPO, preferably with metal filling (EXPENSIVE), but any filling will do if you aren't trying to extract the maximum amount of heat - the cost be damned. They create flat surface with no holes, so no soldering problems whatsoever - beyond those typical for any QFNs.

Unnecessary. With 0.3mm holes the wicking is minimal, and you can pump still pump a bunch of power into the ground plane.
It works for power opamps, transistors, that can dissipate several watts. it worked for TO-263 and other packages, that have been around for ages.

[asmi]

Unnecessary. With 0.3mm holes the wicking is minimal, and you can pump still pump a bunch of power into the ground plane.

Minimal wicking is not the same as no wicking.

It works for power opamps, transistors, that can dissipate several watts. it worked for TO-263 and other packages, that have been around for ages.

Metal-filled VIPPO have much higher thermal conductivity so you can remove more heat from power parts. In most cases that might not be important, but there are cases where it's a major advantage which can make or break the product.

[Doctorandus_P]

I would just mention that the best way to deal with it is to use VIPPO,

I very likely don't agree with this. The "best" engineering solution is one that fits the purpose at the lowest total cost. And having ope via's can be an advantage as I mentioned earlier. Especially with relatively big via's, the gap between the footprint and the pad is very narrow, and it will thus have a stronger capillary effect then the via holes. Power consumption for a LED driver is (very likely) also modest, so there is no need at all to add extra cost in an attempt to "improve" it. It's quite likely that on a 4 layer PCB with a big GND plane under the IC and no thermal vias at all the dissipation is already plenty in this application.

[asmi]

I very likely don't agree with this.

You are welcome to have your own opinion.

The "best" engineering solution is one that fits the purpose at the lowest total cost.

Said who? The best is the best, cost does not matter.

And having ope via's can be an advantage as I mentioned earlier. Especially with relatively big via's, the gap between the footprint and the pad is very narrow, and it will thus have a stronger capillary effect then the via holes. Power consumption for a LED driver is (very likely) also modest, so there is no need at all to add extra cost in an attempt to "improve" it. It's quite likely that on a 4 layer PCB with a big GND plane under the IC and no thermal vias at all the dissipation is already plenty in this application.

Never seen a problem of floating QFNs in the real life. But I did see parts operating much hotter than they are supposed to because too much solder went into thermal vias leading to spotty contact instead of full pad like it should.

[free_electron]

Make a windowpane design with soldermask spokes. 0.3mm vias is large ... 0.25 is recommended. Have a soldermask ring of 0.15mm around each via and use spokes that are 0.1mm.
Example :

These constructions work great to avoid VIPPO.

[tszaboo]

I very likely don't agree with this.

You are welcome to have your own opinion.

The "best" engineering solution is one that fits the purpose at the lowest total cost.

Said who? The best is the best, cost does not matter.

And having ope via's can be an advantage as I mentioned earlier. Especially with relatively big via's, the gap between the footprint and the pad is very narrow, and it will thus have a stronger capillary effect then the via holes. Power consumption for a LED driver is (very likely) also modest, so there is no need at all to add extra cost in an attempt to "improve" it. It's quite likely that on a 4 layer PCB with a big GND plane under the IC and no thermal vias at all the dissipation is already plenty in this application.

Never seen a problem of floating QFNs in the real life. But I did see parts operating much hotter than they are supposed to because too much solder went into thermal vias leading to spotty contact instead of full pad like it should.

You don't even know what the IC does, and how much it dissipates and you want to add copper filled plugged vias to the PCB. This might be a microcontroller, using 3mW of power on average that just happens to come in this package.
I've worked with engineers like  this, they never were able to make compromises in their designs. The designs were simultaneously under and overengineered. And after they left, we had to redo their work, that resulted in products that cost half as much.

[thm_w]

The IC is mentioned in OP: https://www.lumissil.com/assets/pdf/core/IS31FL3239_DS.pdf
Max output 0.9A.

But yeah no idea what dissipation, could be 0.1W could be 1W depends on design, if external resistor is used.

[asmi]

You don't even know what the IC does, and how much it dissipates and you want to add copper filled plugged vias to the PCB. This might be a microcontroller, using 3mW of power on average that just happens to come in this package.

I never mentioned any specific IC, I was talking in generalities.

I've worked with engineers like  this, they never were able to make compromises in their designs. The designs were simultaneously under and overengineered. And after they left, we had to redo their work, that resulted in products that cost half as much.

If only you'd learn reading comprehension instead of arguing with voices in your head instead of the actual person you're talking to...

[Doctorandus_P]

I never mentioned any specific IC, I was talking in generalities.

You did mention defaulting to vippo (regardless of other concerns) and that is just stupid advise.

[asmi]

You did mention defaulting to vippo (regardless of other concerns) and that is just stupid advise.

I did not say "defaulting to vippo", I said it's the best available option if you need the best thermal performance, but I also noted that it's expensive so in many cases it isn't worth the added cost. That said, with JLC offering resin-filled VIPPO for free for 6+ layer PCBs there is little reason not to use them if they are available. And even for 4 layers in some cases it makes sense to pay for VIPPO - for example if your design has 0.5 mm pitch BGAs or lower, because otherwise you simply can not use those devices, and as the time goes on, the trend towards chip-scale packages does not seem to be going anywhere any time soon, so over time VIPPO is turning from "nice to have" luxury option into the key design enabler, meaning those designs just won't be possible without them.

[Doctorandus_P]

You did mention defaulting to vippo (regardless of other concerns) and that is just stupid advise.

I did not say "defaulting to vippo", I said it's the best available option if you need the best thermal performance, but I also noted that it's expensive so in many cases it isn't worth the added cost.

Read your own post again:

I would just mention that the best way to deal with it is to use VIPPO, preferably with metal filling (EXPENSIVE), but any filling will do if you aren't trying to extract the maximum amount of heat - the cost be damned. They create flat surface with no holes, so no soldering problems whatsoever - beyond those typical for any QFNs.

To me, this reads as: "VIPPO is the best" and you don't care about the costs. Apparently something was lost in translation between your brain and your fingers.

The footprint posted by Free_Electron looks good. One of the biggest problems for soldering QFN's are voids on the center pad. Solder paste is about half solder, and half flux, and a part of the flux vaporized, while some stays liquid during soldering. The small dots of solder paste leave channels for outgassing, and open vials can also help to provide a path for outgassing. (I do assume there is a big continuous GND pad in that footprint).

[Swainster]

If there are no specific requirements, I default to encroached vias for this kind of thermal pad. Just watch out for your board manufacturer trying to 'correct' your solder mask during production (probably at least partly my fault for not communicating clearly).

[Skauber]

This turned into quite the debate..

In my application it is driving 21 LEDs, ISET is configured at 23mA, so max sink current would be around 483mA. I dont expect the thermals to be crazy, but I want to do the best I can to control it. At the moment I havent changed anything regarding the solder paste layer, I had a look at it, and it seems the solder paste layer and copper layer is joined in the pad, I cant remove one without removing the other. I still retained the 5 0.3mm vias. While it has been said 0.25mm or 0.2mm are ideal, but manufacturing cost limits me to 0.3mm, and I hope that will be ok, or at least JLC might notify me if they see a problem with it, I estimate it is ready to be sent for manufacturing maybe next week, so still have time to implement any suggested improvements if needed.

[asmi]

In my application it is driving 21 LEDs, ISET is configured at 23mA, so max sink current would be around 483mA. I dont expect the thermals to be crazy, but I want to do the best I can to control it. At the moment I havent changed anything regarding the solder paste layer, I had a look at it, and it seems the solder paste layer and copper layer is joined in the pad, I cant remove one without removing the other. I still retained the 5 0.3mm vias. While it has been said 0.25mm or 0.2mm are ideal, but manufacturing cost limits me to 0.3mm, and I hope that will be ok, or at least JLC might notify me if they see a problem with it, I estimate it is ready to be sent for manufacturing maybe next week, so still have time to implement any suggested improvements if needed.

If you are going to be assembling via JLCPCB, they are going to make a stencil to their standards, so you don't really need to worry about it too much - they know their process and their equipment, and they don't want to deal with QA issues because at the end of the day it costs money, so they will do whatever is in their power (within reason of course) to ensure good results. And the same can be said about most assembly houses - if they know what's good for them, they will insist on making their own stencils for reasons mentioned above.

[Skauber]

Ok, good to know. Its the first time using this type of footprints, so will be a good learning experience.

[free_electron]

vippo is becoming more and more the norm. 10 years ago it was a cost adder cause the lines were not set up for the flow. All the big asian fabs have invested a lot in bringing this mainstream. The move to 0402 and smaller demands via in pad and then you have no other option than to go the VIPPO route. Even with the smallest drilled vias and smallest annular ring , the space required to drop two vias is larger than a 0402 footprint.
Once you go VIPPO you can actually switch to soldermask defined pads and get a double-whammy.

Since the process step is now integrated in the line the cost-adder is minimal (for mass production)

For any board that uses 0.5mm pitch and 0603 or larger VIPPO is not required. Drop below that (0.4mm pitch) and 402 and VIPPO becomes almost mandatory. On 0.35mm pitch 0201 and below (01005 and 00804) you can't escape it. Vippo there becomes laser-drilled, one or two hops deep with the rest mechanically drilled.

Other interesting technology is ELIC : every Layer interconnect. You can go from any layer to any layer ( even odd hops). Only for thin substrates and pretty pricey.

[asmi]

Also because VIPPO frees up the top layer in BGA fanout areas, it enables things like escape routing of internal rows on the top layer and getting rid of vias on those traces, which improves SI for multi-gigabit lines.