Routing multiple memory chips in daisy chain

[joniengr081]

Hi,

The daisy chaining is the act of linking multiple points together in series.

In a linear daisy chain, the first point is connected to a second point, a third point is connected to the second point, and so on until the circuit is returned to ground.

In a ring topology, the points are daisy chained into a ring. Daisy chaining is popular because it saves space.

I am wondering about routing multiple memory chips in daisy chain on PCB layouts. I guess it would be linear daisy chain, right ? For example if there are two DDR3 or DDR4 memory chips and we need to access one memory at a time from processor then we can route data lines from process to first memory chip and then to second memory chip. Is that an example of linear daisy chain ?

[asmi]

For example if there are two DDR3 or DDR4 memory chips and we need to access one memory at a time from processor then we can route data lines from process to first memory chip and then to second memory chip. Is that an example of linear daisy chain ?

That's called "memory rank". Controller is using chip select line to choose which module it wants to talk to.

[joniengr081]

Thanks for reply. I understand memory ranks.

Then I am wondering about how do we route signals on a PCB layout in daisy chain topology. Kindly give me an example. 

[asmi]

For DDRx it's typically done as a "clamshell" design, when ICs belonging to different ranks are directly opposite - rank 0 is on the top side, rank 1 is on the bottom side, using the same vias. Memory controller need to support this feature (because DDRx IC balls are not mirror-symmetric), and many of them do, but not all. Take a look at any DDR3/4/5 dual rank DIMM/SO-DIMM, and you will see what it looks like in the real life. This way stubs are minimized (especially if via-in-a-pad tech used), so there is only a relatively minor signal degradation, though for some controller it can be enough to force lowering operating frequency.

[Doctorandus_P]

The good old (30+years) memory chips were slow enough that routing did not matter much, but with DDR it's quite different. DDR needs careful routing  and bus termination. Dee for example the 48 page pdf below, which is just about "Hardware and Layout Design Considerations for DDR Memory Interfaces".

https://www.nxp.com/docs/en/application-note/AN2582.pdf

Note:
I did not read the document, just found it after a 30second search and skimmed briefly through it.