Simulating a 3 phase motor controller design

[c10yas]

To preface this, this is my first post on the forum and I'm not familiar with all the posting rules. I apologize in advance for any transgressions and welcome feedback.

I have been trying to simulate a 60V 95A wide-bandgap 3phase motor controller using the EPC2053 GaNFET using LTSpice. However, I am having issues with reconciling the theoretical numbers and the simulation outputs. I'm using 4x paralleled FETs on each leg of each half-bridge.
To simulate switching losses, I'm using a double pulse test as described here - https://gansystems.com/wp-content/uploads/2018/05/GN008-GaN_Switching_Loss_Simulation_LTspice_20180523.pdf. I used this to understand the dependence of switching losses on gate current since a paper from TI (http://www.ti.com/lit/an/slyt664/slyt664.pdf) explained the relationship as linear which it clearly wasn't from simple observations. I have attached the graph I got at 80V and 24A
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The losses naturally aren't linear since gate inductance and capacitor charging curves prevent the gate from charging at maximum current the entire time. Notice that the switch-off losses barely reduce, since the majority of the losses come from the Coss charging. 1/2CV^2 gives me an approximate value of 2uJ stored in the Coss cap which lines up with the values calculated. To get realistic switching losses since that is the loss at 80V and 24A, I assumed a linear relationship between Idrain and the losses, therefore, the losses are scaled by 2/pi.

For conduction losses, I take the RMS current of a sine wave peaking at 24A and get 17A as the RMS current through the FET. This current at any point in time is flowing through either the top or bottom fet, resulting in a total conduction loss in the bridge of I^2*R  = 1W.

I wanted to know if the methods I am using to calculate the losses are accurate and if there is any better way of verifying my calculations. I have attempted to create a single-phase inverter that charges an inductor with a sine-shaped current waveform, peaking at 24A at 1ms (250Hz wave). I am still working out the kinks with this but am not sure if this is a good way of doing it, below is an example of a waveform that I get -

Here is the circuit I used

This simulation does not account for Back EMF from the inductor, or that when the sync phase of the lower mosfet is active, the inductor current is reducing in an actual inverter. However, I wasn't sure how to simulate these, and whether they affect the losses in the FETs in a significant manner

I also have another question, as if this post wasn't long enough. How do I calculate the parasitic inductances in the PCB layout? I was using this document(https://www.researchgate.net/publication/324511689_Calculation_of_PCB_Power_Loop_Stray_Inductance_in_GaN_or_High_didt_Applications) to give me an approximate idea of how to calculate it, but if my layout involves visa cutting through the planes and other such stuff, how do I account for these? Do I need to?