I should leave high speed lines on the top layer to avoid vias? Address bus and data bus on the top layer without vias?
What board technology will you use ?
You first need to look at the required impedance for the DDR's and see if you can meet that in terms of line width and spacing on the to layer.
The required trace parameters may be such that you cannot route between the balls of the BGA. You can get away with local discontinuity if it is not too bad and you are not pushing the envelope ( like DDR3 and GDDR5 )
IF that does not work you will need to change board technology and go to a laser drilled board. ( don't be afraid, laser drilling is actually cheaper than mechanical drilling. Mechanical drills can do about 2000 holes an hour or less depending on drill size , Laser drills do the same 2000 holes in a minute . )
Using laser drilling you get to control how deep you burrow.
The advantage is :
-no via stubs so no reflections
-very small via's, that fit in a pad or in a trace, so no discontinuities there... a 4 plug in an 11 mil pad is no problemo for lasers.
once you start burrowing you can be creative with the layer stack . you will have sequential lamination anyway
- top
- prepreg < thin so top will couple to ground
----------------------------------------------
- ground
- prepreg < thin so signal 1 will couple to ground
---------------
- signal 1
- core <-thick so no coupling between signals layers
- signal 2
---------------
- prepreg < thin so the signal 2 will couple to power ( power and ground planes are very low impedant. for all means and purposes a power plane is a ground plane. )
- power
--------------
- prepreg < thin so bottom will couple to power
- bottom
you can burrow from top to signal 1 by placing two laservias on top of each other
same for bottom to signal 2
you can have complete thru-board via's for things like power nets , or you use the buried from signal 1 to signal 2 ( you get that one for free )
if you create the via stacks like snowmen ( and not old fashioned dogbones) you can get tremendous routing density on the signal layers.
This board would be constructed as follows
- double sided core , drill holes , plate , pattern. now you have a panel holding signal 1 and signal 2
- apply prepreg and copper foil above and below, laser drill , plate , pattern . this becomes your planes
- apply prepreg and copper foil above and below. laser drill , mechanical drill for the thru's , plate , pattern. board ready.
so you have two lamination cycles
you can do 3 if needed but production time increases with each lamination cycle , it is cheaper to build multiple cores in that case.
You really don't want to be faffing about with simply 6 layer thru-only boards. Modern SOc's are designed for HDI technology ( Laser / blind and buried ). It solves so many problems ( impedance, routing density , connectivity ) in an elegant cost effective way.
But you DO need the tools that understand this technology and help you.. otherwise it's all sliderules and chalkboard ...
so first : figure out your impedances and margin, derive from that the trace widths and clearances and see if you can break out the SOC.
If not , adjust the buildup until you get something that works. if you can't make it work : switch to HDI (High density interconnect , basically laservia's in a blind and buried stackup) to solve the problem.