A very pretty chip; the STM32L162RD

[techman-001]

These are some pics I took with my cheap USB microscope, so they are not that special, but hopefully you’ll get the idea.

This chip has been sitting on my bench for a few months, so I cleaned it as best I could with Metholated Spirits before taking the pics below.

The actual chip came from arrow.com where I purchased 10 units for $0.90 AUD each as they were ‘overstocked’.

The package is a WLCSP64 and is approximately 4.5 mm x 4.5 mm on each side and 0.38 mm thick with 64 solder blobs for pins (BGA).

The entire chip is silicon and the size of the actual DIE, there is no plastic or any other case material, and no copper pins.

This to my mind represents the state of the art in miniaturization, where the connections are via solder blobs onto metallized tracks which connect to the pads on the die periphery.

When I looked at this chip under my 40x microscope it took my breath away because I could see under the silver and gold metallization into the chip itself. That’s right, the parallel lines which look a dull gold in my picture, looked shiny and like they are made of solid GOLD in the microscope.

I’ve never seen anything as breathtaking as this before and I’m used to looking at chips with microscopes and lighting that make the “wire bonding” wires look the size of lamp posts.

Capability:
This STM32L162RD is just JAM PACKED with peripherals, it is mind boggling!  https://www.st.com/resource/en/datasheet/DM00039232.pdf

        Ultra-low-power 32-bit MCU Arm® Cortex®-M3
        384KB Flash
        48KB SRAM
        12KB EEPROM
        LCD, USB, ADC, memory I/F, AES
        Low Power, 305 nA Standby mode

So is it the perfect chip ?

Probably not, but it's sure pretty, and perhaps represents the state of the art.

This type of package is quite fragile, open to light so needs to be sealed underneath after reflow soldering. The solder balls are VERY close to the silver tracks so I imagine BEST BGA practices would be needed to use it.

I could easily scrape the silver metallization off the base with a knife using virtually no force, tho this is not a fair criticism because I’m a 100 ton giant compared to this tiny silicon chip.

Note: I'm not connected to STM or arrow.com in any way and I receive no payment of any kind from them. I do however love STM32 MCU's.

[Brutte]

EEVblog #900 topic.

The L162 is a feature-rich version of L152 which is a feature-rich version of L100.
WLCSP 0.4 are not for faint-hearted - if you want to do a development then you'd better buy several chips in LQFP64. These packages require at least HDI technology - forget about standard multilayer PCB.

[Vcky_electro]

EEVblog #900 topic.

The L162 is a feature-rich version of L152 which is a feature-rich version of L100.
WLCSP 0.4 are not for faint-hearted - if you want to do a development then you'd better buy several chips in LQFP64. These packages require at least HDI technology - forget about standard multilayer PCB.

Yes. These packages are very tiny. While handling these chips we use micro vias for the connection (HDI- High density interconnect technology).

[mikerj]

If you think that's a small device, take a look at the MAX32660, a Cortex M4 part (with FPU), 256k flash, 96k SRAM, 96MHz clock all in a 16 bump WLP package measuring 1.6mm x 1.6mm.

These tiny WSCP parts are widespread in the products we design, along with the 01005 and 0201 passives.  I just wish my aging eyesight was a bit better and my hands a little less shaky; just soldering fine enameled copper wire onto components for debugging is hard enough.

[Brutte]

This makes me wonder - HDI is quite an expensive technology, both in development and mass production, when compared to multilayer.
What is the point offering WLCSP 0.4 chip with LCD glass driver?
One is for size constrained applicaiton and the other one is for relatively huge stuff.
It is like selling a nA chip intended to be mains powered.

[daqq]

Yup, WLCSP packages are getting silly :-)

Probably not, but it's sure pretty, and perhaps represents the state of the art.

True for end user (us) packaging, not true for the industry packaging. Multi chip devices, such as some FPGAs that use Stacked Silicon Interconnect have an even finer pitch and connect to a passive silicon interposer (see: http://www.swtest.org/swtw_library/2013proc/PDF/SWTW13-25.pdf , page 11).

What is the point offering WLCSP 0.4 chip with LCD glass driver?
One is for size constrained applicaiton and the other one is for relatively huge stuff.

First of all, I'm guessing that the die is the same, aside from the final processing for all package options, so it's impossible/pointless to remove/disable hardware. Second, there's probably some niche application, where it's a reasonable combination - basically, if you can, why not slap it in there.

Also, there's the other thing, if you can have a board technology that's 2x as expensive per square centimeter, but you can fit the same design onto a board that's 1/4th of the size, you still end up getting a cheaper board. Why not have a small board driving a big LCD?

[techman-001]

it's sure pretty, and perhaps represents the state of the art.

True for end user (us) packaging, not true for the industry packaging. Multi chip devices, such as some FPGAs that use Stacked Silicon Interconnect have an even finer pitch and connect to a passive silicon interposer (see: http://www.swtest.org/swtw_library/2013proc/PDF/SWTW13-25.pdf , page 11).

Just wow, thanks for the pdf link which is so informative, and it's already 6 years old !