Anyone still using Mikrotik rb532A? (2006, mips32le router)

[DiTBho]

When it appeared in 2006, it was the era of Linux v2.6, v2.6.22 to v2.6.32 were the kernels of greatest interest and support, especially by OpenWRT.
When I write on { NetBSD, Linux/MIPS, ... } ML ... nobody replies. Sounds abandoned platform.

Then came the RPI and other cheaper SBCs, and the rb532a took a back seat until the END of LIFE declared by the manufacturer.

I can boot kernel 6.0x, but there are still many unresolved issues.

First of all, the firmware has some undocumented quirks, sometimes it refuses to tftpboot elf binaries, but it doesn't explain why, nor does it provide an error message that can help.

Second, the firmware refuses to accept some Microdrive, it doesn't explain why, it only says "CF not present", while you hear the motor spinng down.

Third, the firmware requires you partition the NAND flash into two slices.

Code: [Select]

dev:    size   erasesize  name
mtd0: 00400000 00020000 "Routerboard NAND boot"
mtd1: 07c00000 00020000 "rootfs"
The first slice must be 4Mbyte size, and must be "yaffs" formatted. The linux kernel must be renamed "kernel", otherwise it won't load it.

Here the first problem: 4-Mbyte is too small for a modern kernel v6, which is usually not less than 7-Mbyte with the minimal configuration.
Secondly, the "yaffs" (flash-oriented) filesystem was never included in the linux kernel, worse still it is no longer supported since a while.


Anyone still using it? 

[DiTBho]

based on IDT-79RC32434.
A few interesting posts about its performance here on the Forum.


edit:
Latest Rooterboot with fixes mentioned specifically for rb532a is v2.18, see changelog

[DiTBho]

"kernel out of range" during Tftpboot

This error is not related to the binary dimension of the elf.
I have not yet figured out what it is related to.

Code: [Select]

RouterBOOT booter 2.8

RouterBoard 532A

CPU frequency: 399 MHz
  Memory size:  64 MB

Press any key within 2 seconds to enter setup..
trying bootp protocol... OK
transfer started
.......................................................... transfer
ok, time=2.76s
setting up elf image... kernel out of range
kernel loading failed


[Nominal Animal]

This error is not related to the binary dimension of the elf.
I have not yet figured out what it is related to.

I believe RouterBOOT 2.8 is very limited in what address ranges it can load a kernel at, and the "kernel out of range" error indicates the kernel image wants to be loaded outside that range.  Simply put, it's RouterBOOT 2.8 being stupidly limited/limiting.

(If the kernel image is compressed, then it could also be that RouterBOOT loads the compressed image to the same address range as the kernel wants to be decompressed to.)

I fear your only options are to play with the kernel base address (CONFIG_PHYSICAL_START).  I don't know if RouterBOOT allows changing where it loads the compressed image, what the 4MB range it has reserved for that is.

[DiTBho]

I believe RouterBOOT 2.8 is very limited in what address ranges it can load a kernel at, and the "kernel out of range" error indicates the kernel image wants to be loaded outside that range.  Simply put, it's RouterBOOT 2.8 being stupidly limited/limiting.

Yup, RouterBoot is full of quirks, and the user manual doesn't say anything.
I emailed severally and several times to Mikrotik, they never answered.

Over time, and by trying it myself, I discovered that it expects

• The first partition of the Microdrive/Compact Flash formatted with PC-partition scheme, the first partition must have part_type=27, contaning no filesystem, and the size must be equal to 8Mbyte, it will "raw load" into ram, and executed.
• The flash must be partitioned with a fixed scheme, and must contain two YaFFs v1 (v2 won't work) partitions. The first partition must be equal to 4Mbyte and must contain a file "kernel"
• Not yet understood if the tftpboot is limited below 8Mbyte, not clear, sometimes it works, sometimes it does not

I could only speculate that RouterBoot opens an 8Mbyte window in the way it addresses RAM for the application.elf (the linux kernel in my case) to load and boot 

Unfortunately these things are not written anywhere, and that ... even in OpenWRT have never been clear.
Patches are confusing, and, worse still, patches don't come with a note in their header.

[DiTBho]

If the kernel image is compressed, then it could also be that RouterBOOT loads the compressed image to the same address range as the kernel wants to be decompressed to.

no, it's not compressed. Compression is one of the things that has never worked properly in the last ~20 years (2006-2025) on this board, and I don't have time to debug it at the moment.

Better to run the kernel uncompressed, and eliminate another source of trouble.

[DiTBho]

I fear your only options are to play with the kernel base address (CONFIG_PHYSICAL_START).

This is one of the points of confusion, there are patches that force the first flash partition to 8Mbyte (kernel bult-in).
I don't know if this thing works as a hack or if it ever worked.
I've never seen it work in person as OpenWRT never officially supported it.
There were random posts around the old web, 10 years ago, from random hackers, never confirmed.

In any case it is not clear if there is really a constant to define that loading window.
We know that every now and then something works, but it's all random.
Except loading from the CF, which works quite reliable up to 8Mbyte.

What worked, at the time, were kernels with sizes of 900Kbyte or at most 2.4Mbyte.

I don't know if RouterBOOT allows changing where it loads the compressed image, what the 4MB range it has reserved for that is.

My speculation, I guess is built-in defined in RouterBOOT.

Frankly, I wish I could replace RouterBOOT with u-boot 

[Nominal Animal]

I fear your only options are to play with the kernel base address (CONFIG_PHYSICAL_START).

This is one of the points of confusion, there are patches that force the first flash partition to 8Mbyte (kernel bult-in).

CONFIG_PHYSICAL_START defines where the kernel will reside in physical RAM, it doesn't affect storage at all (even though the flash storage is addressed as memory also).

I can't tell from OpenWRT whether OpenWRT 18.06.9 is the last version supported, or if you need to go back to Backfire 10.03.1.  The OldWiki contains related info.  I would definitely test if these boot, and whether they have any unacceptable bugs in your use.  DD-WRT 2006 - 1203 should also support RB532 (but unsure of RB532A); the latest sources for RB5xx were in  revision 22682 (unchanged since 4767, I believe).  The old docs are here.

(This is exactly why I appreciate companies like AMD, Intel, RockChip, Samsung, et cetera, that push support of their CPUs to vanilla Linux kernel support, instead of separate patches somewhere.  Just think if you had someone collect and preserve these "historical" patches and their documentation at kernel.org, say in a timeline-like fashion you could limit to a specific architecture?  Not just for those working on older devices, but also for recording the history of kernel patches for various devices.)

[DiTBho]

CONFIG_PHYSICAL_START defines where the kernel will reside in physical RAM, it doesn't affect storage at all (even though the flash storage is addressed as memory also).

Maybe I didn't explain myself

All the kernels I've compiled have the same value of CONFIG_PHYSICAL_START.
However:

• the slice0 of the flash can't be bigger than 4Mbyte -> you cannot physically store any kernel bigger than 4MByte in that slice.
  What I have stored here has always started
• There is no documentation telling you cannot tftpboot an elf bigger than 8MByte, but in practice it always fails. Smaller kernels usually boot.
  Except, kernels compiled with a built-in initramfs. They usually fail, no matter if smaller than 8Mbyte -> weird
• There is no documentation telling you cannot boot an elf bigger than 8MByte from the CF, but in practice it always fails, and you have to make the partition no bigger than 8Mbyte. Smaller kernels usually boot from the CF, including those compiled with a built-in ramrootfs

So ... same kernel, different booting methods, different results.

[DiTBho]

I have several booting kernels

• kernel-2.06.032, legacy, it needs gcc-v4, it supports Yaffs-v1 -> size=~3.5Mbyte, stable
• kernel-2.06.037, legacy, it needs gcc-v4, it supports Yaffs-v1 -> size=~3.5Mbyte, stable
• kernel-4.04.197, can be compiled with modern gcc, it does not support Yaffs-v1 -> size=~7.3Mbyte, stable
• kernel-6.02.002, can be compiled with modern gcc, it does not support Yaffs-v1 -> size=~7.7Mbyte, experimental

(optimized for space)

However, I'm tired of wasting time with RooterBoot!
I'm writing my own bootloader that will load the linux kernel.

This way I bring the situation back to a deterministic state, where I know what happens under the hood.

Today I've already written the bootloader skeleton and verified that RooterBoot loads it from the network and from flash, and starts it.

It works 

In the next few days I'll implement the built-in lan, a udp/ip stack for the tftpboot, and a driver to access the CF.
Different architecture, but for sure I will reuse some of the C code I wrote for the Soekris net5501(1) bootloader.

(1) AMD Geode, x86-compatible

[DiTBho]

This is the working status, after two days of work, just to get a 10 year old kernel back on its feet
Yaffs-v1 finally 100% works 

Code: [Select]

# mount
/dev/sda3 on / type ext2 (rw,relatime,errors=continue,user_xattr)
none on /sys type sysfs (rw,relatime)
none on /proc type proc (rw,relatime)
none on /dev/pts type devpts (rw,relatime,mode=600,ptmxmode=000)
/dev/mtdblock0 on /mnt/mtd_p0 type yaffs (rw,relatime)
/dev/mtdblock1 on /mnt/mtd_p1 type yaffs (rw,relatime)

A lot of troubles to get at this point

• a 10 years old OpenWrt-dev-kit does not work on modern GNU/linux, due to a lot of incompatibilities with the ecosystem, stating from gcc, to ncurses, to Makefiles, to perl, a lot of things have changed in 10 years and ... a I have a long list of patches that I created on the path
  
• getting started with yaffs-v1 is... hell. It's very difficult to be integrated into the kernel, confusing patches, too many revisions, no clean documentation

Code: [Select]

macmini2-intel kernel-2.06.032-mips-rb532 # ./mybuild-2024 2
[step2] compiling
kernel-2.06.032(mips/rb532)
| experimental Yaffs-v1
| Use a Linux compiler or give up
| Use gcc v4.* or give up
toolchain(mipsle-unknown-linux-gnu:2.21.1/4.5.3)
-----------------------------------------------
checking myhost as qualified_host ... success
checking .config ... success
checking blobs ... success
-----------------------------------------------
gadget_to_do(build) ... overlay/build
cleaning ............. done
gadget_to_do(clean) ... kernel/clean
app_machine=rb532
building kernel ... success
-----------------------------------------------
gadget_to_do(binary) ... overlay/binary
gadget_to_do(sweep) ... kernel/sweep
app_body    =kernel.elf
app_size    =3197011 byte
app_size_max=3900000 byte
checking size ... passed
gadget_to_do(binary_report) ... kernel/binary_report

As you can see, the final elf is smaller than 4Mbyte, so it can be copied to the first MTD slice mtd0

Code: [Select]

uc-rb532 /mnt/mtd_p1 # cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00400000 00020000 "Routerboard NAND boot"
mtd1: 07c00000 00020000 "rootfs"

mtd0 (/dev/mtdblock0) is 4Mbyte

Code: [Select]

major minor  #blocks  name
  31        0       4096 mtdblock0
  31        1     126976 mtdblock1
   8        0     990864 sda
   8        1       4336 sda1
   8        2      16624 sda2
   8        3     969360 sda3


Code: [Select]

mknod /dev/mtdblock0 b 31 0
mknod /dev/mtdblock1 b 31 1


Code: [Select]

rb532 fix partition-info, set mtd0 to 8Mbyte, experimental
--- arch/mips/rb532/devices.c
+++ arch/mips/rb532/devices.c
@@ -186,11 +186,11 @@ static struct platform_device nand_slot0

 static struct mtd_partition rb532_partition_info[] = {
        {
-               .name = "Routerboard NAND boot",
+               .name = "kernel",
                .offset = 0,
-               .size = 4 * 1024 * 1024,
+               .size = 8 * 1024 * 1024,
        }, {
-               .name = "rootfs",
+               .name = "rootfs", /* ~ (128-8)8MB = 120MB */
                .offset = MTDPART_OFS_NXTBLK,
                .size = MTDPART_SIZ_FULL,
        }

This is the patch I was talking about to resize /dev/mtdblock0 to 8Mbyte.

Not yet tried 

[DiTBho]

I am working on Vanilla kernel v2.6.32, integrating patches from OpenWRT, and my own patches.
The rootfs is made by Catalyst(Gentoo), using an old (2009) uclibc stage 1-3.

I also have my super-stable 2009 stage4/glibc with gcc v4.1.2, and the new 2020 stage4/glibc with gcc-v7.
The last one is more than suitable also for the rbm33g router

-

In the meantime I continue to develop my bootloader too.

It will be installed in the first slice of the flash, mtd0
But I need Yaffs-v1 to do this because Routerboot at startup expects ...
... the flash to be partitioned as above and the first partition to be formatted Yaffs-v1

Yaffs-v2 is not compatible with Yaffs-v1 

[DiTBho]

Anyone use it? Anyone interested?
Let me know 

further discussion on the development of { mtd, disk }, see here

[DiTBho]

The rb532a doesn't accept some MicroDrives.
There is no documentation about.

It seems the board turns off the motors if the MicroDrives doesn't match some criteria.

I don't know which gpio/port controls the motor enable 

[DiTBho]

So, I traded in some of my old Turbo Pascal programming books for an rb564 daughterboard, which adds six Via-Rhine ethernet chips, turning the rb532a into a "serious" router!

Code: [Select]

Board Info:

        Board type: 532A
  Firmware version: 2.12
     CPU frequency: 399 MHz
       Memory size: 64 MB
  eth1 MAC address: 00:0C:42:0E:9F:1B
  eth2 MAC address: 00:0C:42:0E:9F:1C
  eth3 MAC address: 00:0C:42:0E:9F:1D
-------------------------------------------------
  eth4 MAC address: 00:0C:42:03:58:FB
  eth5 MAC address: 00:0C:42:03:58:FC
  eth6 MAC address: 00:0C:42:03:58:FD
  eth7 MAC address: 00:0C:42:03:58:FE
  eth8 MAC address: 00:0C:42:03:58:FF
  eth9 MAC address: 00:0C:42:03:59:00

However... there is one big problem with PCI ...

Code: [Select]

eth0: korina
via-rhine 0000:00:02.0: enabling device (0080 -> 0083)
via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142
via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:00:03.0: enabling device (0080 -> 0083)
via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143
via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
pci 0000:00:06.0: enabling device (0000 -> 0003)
via-rhine 0000:01:02.0: enabling device (0080 -> 0083)
via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141
via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:03.0: enabling device (0080 -> 0083)
via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143
via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:04.0: enabling device (0080 -> 0083)
via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140
via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:05.0: enabling device (0080 -> 0083)
via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142
via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:06.0: enabling device (0080 -> 0082)
via-rhine 0000:01:06.0: Insufficient PCI resources, aborting
via-rhine: probe of 0000:01:06.0 failed with error -5
via-rhine 0000:01:07.0: enabling device (0080 -> 0082)
via-rhine 0000:01:07.0: Insufficient PCI resources, aborting
via-rhine: probe of 0000:01:07.0 failed with error -5

rb532 / # ifconfig -a
eth0      Link encap:Ethernet  HWaddr 00:0c:42:0e:9f:1b
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:40

eth1      Link encap:Ethernet  HWaddr 00:0c:42:0e:9f:1c
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth2      Link encap:Ethernet  HWaddr 00:0c:42:0e:9f:1d
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth3      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fb
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth4      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fc
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth5      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fd
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth6      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fe
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

lo        Link encap:Local Loopback
          LOOPBACK  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

rb532 / #

eth0 is the SoC built-in ethernet.
eth1 and eth2 are on the rb532
eth3 to eth6 are on the rb564 expansion

but some of the new ethernets { eth7, eth8 } on the rb564 expansion are not initiazlied since the they return "Insufficient PCI resources, aborting"

... umm, same behavior from kernel 2.6.32 to 6.02.* 

[Nominal Animal]

Dammit, that looks annoying, considering rb564 is specifically suggested as an add-on for rb532a.

Do you happen to have the RouterOS (from Mikrotik) license for the rb532a, to compare the (verbose) kernel log and reports to?  6.32.2 (2015-Sep-17 15:20) is the latest version (routeros, packages; but also see www.mikrotik-software.de/downloads/) with mipsle support, I believe.  As I understand it, it should have full support for rb564.  I suspect they do it by somehow overlapping the PCI resources, perhaps with kernel driver options.

Heh, your kernel questions regarding rb532a pop up at lore.kernel.org/linux-mips.vger.kernel.org if one does a related search for Device Tree and such. 

(I've been seriously eyeing Radxa Rock 3B, with two GbE, a M.2 B-key with SIM socket (I'll need a plain passive mini-PCIe-to-M.2-B-key adapter though), and a M.2 M-key for NVMe on the backside.  Rock 5 ITX and Rock 5T would be even nicer, dual NVMes and all, but they're outside my meager budget.  This is to replace the Mikrotik RBM33G with MT7621A/MMIPS I have, being a 4G/LTE router with security cam storage on 1TB NVMe.  The additional benefit with the Rock 3B is that it has a HDMI connector for a TV for nontechnical users to browse the stored footage.  Anyway, if you only have an USB 2.0 connection, ADT-Link WS17 is perfect for a mini-PCIe 4G/5G/LTE modem: the documentation includes the schematic, so one can up the voltage to 3.8V for lower current with higher power antennas by just replacing one SMD resistor! For USB 3.0, one must use WS18, though.)

[DiTBho]

Dammit, that looks annoying, considering rb564 is specifically suggested as an add-on for rb532a.

yup, very annoying considering how expensive the rb564 was (>>90 euro), also RouterOS is based on the Linux kernel, therefore I was expecting less troubles.
The rb532a is full or problems, not only in recent kernel v6.02 branches, but also in those from the days (2006--2009) when rb532a was new.
OpenWRT has been the only source of patches, it has done a great job, but you can expect only basic stuff to work.

Do you happen to have the RouterOS (from Mikrotik) license for the rb532a, to compare the (verbose) kernel log and reports to?

I have two rb532a boards

• board#0, fw-v2.8, bought in 2008, but I erased the NAND flash many years ago
• board#1, fw-v2.12, fresh bought, 20 days ago, never used, routerOS should be in the NAND flash

This is a board in a sealed bag, unopened stock without box. There is no paper support included.
I don't have any password/doc/whatever/license for RouterOS.

I bought a second board because #0 has been working for many many hours
           MTBF(2025 - 2008) = 
I've done everything with it, several thousand experiments, and I think it might die.
I'm mostly concerned about the capacitors, but also the connector part.

In addition to this, having two allows me to test solutions in parallel.

• #a - On one side the linux kernel, on the other the monitor I'm writing
• #b - On one side the linux kernel without the rb564, on the other the linux kernel with the rb564

[DiTBho]

Heh, your kernel questions regarding rb532a pop up at lore.kernel.org/linux-mips.vger.kernel.org if one does a related search for Device Tree and such. 

... feeling of abandonment, no one responding.
I also tried to contact the names of the people I see signing the patches directly.
No response.

Dunno why 

Radxa Rock 3B [..] to replace the Mikrotik RBM33G

The rbm33g is much much faster than the rb532a, however it doesn't have the same charm.
but it is the perfect "next step" with MIPS routers.

I mean, if you want to write your own OS_less application, the rbm33g adds two cores to manage.
Two cores means more complexity.

[DiTBho]

the Ethernet chips on the rb564 are managed by drivers/net/ethernet/via/via-rhine.c (torvalds' linux github)

[Nominal Animal]

Have you

• Compiled a test kernel with CONFIG_VIA_RHINE_MMIO?
• Modified the error to
      dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n", pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);
  ?
• Disabled the sanity check that emits the error?

in drivers/net/ethernet/via/via-rhine.c?

I think 1. does not changes anything; that 2. would be informative; and that 3. might actually get it to work.


For clarity, it would be useful to move the error to the actual pci region requests, ie. change the entire function into

Code: [Select]

static int rhine_init_one_pci(struct pci_dev *pdev,
      const struct pci_device_id *ent)
{
struct device *hwdev = &pdev->dev;
int rc;
long pioaddr, memaddr;
void __iomem *ioaddr;
int io_size = pdev->revision < VTunknown0 ? 128 : 256;

/* This driver was written to use PCI memory space. Some early versions
 * of the Rhine may only work correctly with I/O space accesses.
 * TODO: determine for which revisions this is true and assign the flag
 * in code as opposed to this Kconfig option (???)
 */
#ifdef CONFIG_VIA_RHINE_MMIO
u32 quirks = rqNeedEnMMIO;
#else
u32 quirks = 0;
#endif

rc = pci_enable_device(pdev);
if (rc)
goto err_out;

if (pdev->revision < VTunknown0) {
quirks |= rqRhineI;
} else if (pdev->revision >= VT6102) {
quirks |= rqWOL | rqForceReset;
if (pdev->revision < VT6105) {
quirks |= rqStatusWBRace;
} else {
quirks |= rqIntPHY;
if (pdev->revision >= VT6105_B0)
quirks |= rq6patterns;
if (pdev->revision >= VT6105M)
quirks |= rqMgmt;
}
}

pioaddr = pci_resource_start(pdev, 0);
memaddr = pci_resource_start(pdev, 1);

pci_set_master(pdev);

rc = pci_request_regions(pdev, DRV_NAME);
if (rc) {
dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n",
                         pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);
goto err_out_pci_disable;
        }

ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
if (!ioaddr) {
rc = -EIO;
dev_err(hwdev,
"ioremap failed for device %s, region 0x%X @ 0x%lX\n",
dev_name(hwdev), io_size, memaddr);
goto err_out_free_res;
}

enable_mmio(pioaddr, quirks);

rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
if (rc)
goto err_out_unmap;

rc = rhine_init_one_common(&pdev->dev, quirks,
   pioaddr, ioaddr, pdev->irq);
if (!rc)
return 0;

err_out_unmap:
pci_iounmap(pdev, ioaddr);
err_out_free_res:
pci_release_regions(pdev);
err_out_pci_disable:
pci_disable_device(pdev);
err_out:
return rc;
}
If that causes the last two Ethernet interfaces to fail with ioremap failed, or the two lock up during operation, a (better!) possibility is that the fourth interface per chip can still be used in PIO mode:

Code: [Select]

static int rhine_init_one_pci(struct pci_dev *pdev,
      const struct pci_device_id *ent)
{
struct device *hwdev = &pdev->dev;
int rc;
long pioaddr, memaddr;
void __iomem *ioaddr;
int io_size = pdev->revision < VTunknown0 ? 128 : 256;

/* This driver was written to use PCI memory space. Some early versions
 * of the Rhine may only work correctly with I/O space accesses.
 * TODO: determine for which revisions this is true and assign the flag
 * in code as opposed to this Kconfig option (???)
 */
#ifdef CONFIG_VIA_RHINE_MMIO
u32 quirks = rqNeedEnMMIO;
#else
u32 quirks = 0;
#endif

rc = pci_enable_device(pdev);
if (rc)
goto err_out;

if (pdev->revision < VTunknown0) {
quirks |= rqRhineI;
} else if (pdev->revision >= VT6102) {
quirks |= rqWOL | rqForceReset;
if (pdev->revision < VT6105) {
quirks |= rqStatusWBRace;
} else {
quirks |= rqIntPHY;
if (pdev->revision >= VT6105_B0)
quirks |= rq6patterns;
if (pdev->revision >= VT6105M)
quirks |= rqMgmt;
}
}

        // If MMIO mapping is not possible, use PIO.
        if ((pci_resource_len(pdev, 0) < io_size) ||
    (pci_resource_len(pdev, 1) < io_size))
quirks |= rqNeedEnMMIO;

pioaddr = pci_resource_start(pdev, 0);
memaddr = pci_resource_start(pdev, 1);

pci_set_master(pdev);

rc = pci_request_regions(pdev, DRV_NAME);
if (rc) {
dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n",
                         pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);
goto err_out_pci_disable;
        }

ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
if (!ioaddr) {
rc = -EIO;
dev_err(hwdev,
"ioremap failed for device %s, region 0x%X @ 0x%lX\n",
dev_name(hwdev), io_size, memaddr);
goto err_out_free_res;
}

enable_mmio(pioaddr, quirks);

rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
if (rc)
goto err_out_unmap;

rc = rhine_init_one_common(&pdev->dev, quirks,
   pioaddr, ioaddr, pdev->irq);
if (!rc)
return 0;

err_out_unmap:
pci_iounmap(pdev, ioaddr);
err_out_free_res:
pci_release_regions(pdev);
err_out_pci_disable:
pci_disable_device(pdev);
err_out:
return rc;
}Note that it has been decades since I last played with Via ethernet drivers, so I could be way off base here.  I do not believe the above can harm anything, though, because it just omits the "sanity check" and last one conditionalizes the PIO option.

I did find a datasheet for VT6105M, and it is limited to 256 PCI addresses; and I suspect the PIO workaround is quite possible the solution Mikrotik used.

Oh, and note that AFAIK RouterOS has a 24-hour/30-day trial you might be able to use with e.g. 6.32.2.

[DiTBho]

Compiled a test kernel with CONFIG_VIA_RHINE_MMIO?

does not changes anything

[DiTBho]

For clarity, it would be useful to move the error to the actual pci region requests, ie. change the entire function into

Code: [Select]

static int rhine_init_one_pci(struct pci_dev *pdev,
      const struct pci_device_id *ent)
{
struct device *hwdev = &pdev->dev;
int rc;
long pioaddr, memaddr;
void __iomem *ioaddr;
int io_size = pdev->revision < VTunknown0 ? 128 : 256;

/* This driver was written to use PCI memory space. Some early versions
 * of the Rhine may only work correctly with I/O space accesses.
 * TODO: determine for which revisions this is true and assign the flag
 * in code as opposed to this Kconfig option (???)
 */
#ifdef CONFIG_VIA_RHINE_MMIO
u32 quirks = rqNeedEnMMIO;
#else
u32 quirks = 0;
#endif

rc = pci_enable_device(pdev);
if (rc)
goto err_out;

if (pdev->revision < VTunknown0) {
quirks |= rqRhineI;
} else if (pdev->revision >= VT6102) {
quirks |= rqWOL | rqForceReset;
if (pdev->revision < VT6105) {
quirks |= rqStatusWBRace;
} else {
quirks |= rqIntPHY;
if (pdev->revision >= VT6105_B0)
quirks |= rq6patterns;
if (pdev->revision >= VT6105M)
quirks |= rqMgmt;
}
}

pioaddr = pci_resource_start(pdev, 0);
memaddr = pci_resource_start(pdev, 1);

pci_set_master(pdev);

rc = pci_request_regions(pdev, DRV_NAME);
if (rc) {
dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n",
                         pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);
goto err_out_pci_disable;
        }

ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
if (!ioaddr) {
rc = -EIO;
dev_err(hwdev,
"ioremap failed for device %s, region 0x%X @ 0x%lX\n",
dev_name(hwdev), io_size, memaddr);
goto err_out_free_res;
}

enable_mmio(pioaddr, quirks);

rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
if (rc)
goto err_out_unmap;

rc = rhine_init_one_common(&pdev->dev, quirks,
   pioaddr, ioaddr, pdev->irq);
if (!rc)
return 0;

err_out_unmap:
pci_iounmap(pdev, ioaddr);
err_out_free_res:
pci_release_regions(pdev);
err_out_pci_disable:
pci_disable_device(pdev);
err_out:
return rc;
}

CONFIG_VIA_RHINE_MMIO disabled

Code: [Select]

PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]
pci_bus 0000:00: root bus resource [io  0x18800000-0x188fffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [111d:0000] type 00 class 0x000000
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]
pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
pci 0000:00:02.0: [1106:3106] type 00 class 0x020000
pci 0000:00:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:02.0: supports D1 D2
pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:03.0: [1106:3106] type 00 class 0x020000
pci 0000:00:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:03.0: supports D1 D2
pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000
pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]
pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]
pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]
pci 0000:00:06.0: [3388:0031] type 01 class 0x060400
pci 0000:00:06.0: supports D1 D2
pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hot
pci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci_bus 0000:01: extended config space not accessible
pci 0000:01:02.0: [1106:3106] type 00 class 0x020000
pci 0000:01:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:02.0: supports D1 D2
pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:03.0: [1106:3106] type 00 class 0x020000
pci 0000:01:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:03.0: supports D1 D2
pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:04.0: [1106:3106] type 00 class 0x020000
pci 0000:01:04.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:04.0: supports D1 D2
pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:05.0: [1106:3106] type 00 class 0x020000
pci 0000:01:05.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:05.0: supports D1 D2
pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:06.0: [1106:3106] type 00 class 0x020000
pci 0000:01:06.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:06.0: supports D1 D2
pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:07.0: [1106:3106] type 00 class 0x020000
pci 0000:01:07.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:07.0: supports D1 D2
pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3cold
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]
pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]
pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]
pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]
pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18800fff]
pci 0000:00:02.0: BAR 0: assigned [io  0x18801000-0x188010ff]
pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]
pci 0000:00:03.0: BAR 0: assigned [io  0x18801400-0x188014ff]
pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]
pci 0000:01:02.0: BAR 0: assigned [io  0x18800000-0x188000ff]
pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]
pci 0000:01:03.0: BAR 0: assigned [io  0x18800400-0x188004ff]
pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]
pci 0000:01:04.0: BAR 0: assigned [io  0x18800800-0x188008ff]
pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]
pci 0000:01:05.0: BAR 0: assigned [io  0x18800c00-0x18800cff]
pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]
pci 0000:01:06.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:06.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]
pci 0000:01:07.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:07.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]
pci 0000:00:06.0: PCI bridge to [bus 01]
pci 0000:00:06.0:   bridge window [io  0x18800000-0x18800fff]
pci 0000:00:06.0:   bridge window [mem 0x50000000-0x500fffff]


Code: [Select]

via-rhine 0000:00:02.0: enabling device (0080 -> 0083)
via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142
via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:00:03.0: enabling device (0080 -> 0083)
via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143
via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
pci 0000:00:06.0: enabling device (0000 -> 0003)
via-rhine 0000:01:02.0: enabling device (0080 -> 0083)
via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141
via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:03.0: enabling device (0080 -> 0083)
via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143
via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:04.0: enabling device (0080 -> 0083)
via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140
via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:05.0: enabling device (0080 -> 0083)
via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142
via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:06.0: enabling device (0080 -> 0082)
via-rhine 0000:01:06.0: ioremap failed for device 0000:01:06.0, region 0x100 @ 0x50000400
via-rhine: probe of 0000:01:06.0 failed with error -5
via-rhine 0000:01:07.0: enabling device (0080 -> 0082)
via-rhine 0000:01:07.0: ioremap failed for device 0000:01:07.0, region 0x100 @ 0x50000500
via-rhine: probe of 0000:01:07.0 failed with error -5


-----
CONFIG_VIA_RHINE_MMIO enabled

Code: [Select]

PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]
pci_bus 0000:00: root bus resource [io  0x18800000-0x188fffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [111d:0000] type 00 class 0x000000
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]
pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
pci 0000:00:02.0: [1106:3106] type 00 class 0x020000
pci 0000:00:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:02.0: supports D1 D2
pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:03.0: [1106:3106] type 00 class 0x020000
pci 0000:00:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:03.0: supports D1 D2
pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000
pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]
pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]
pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]
pci 0000:00:06.0: [3388:0031] type 01 class 0x060400
pci 0000:00:06.0: supports D1 D2
pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hot
pci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci_bus 0000:01: extended config space not accessible
pci 0000:01:02.0: [1106:3106] type 00 class 0x020000
pci 0000:01:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:02.0: supports D1 D2
pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:03.0: [1106:3106] type 00 class 0x020000
pci 0000:01:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:03.0: supports D1 D2
pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:04.0: [1106:3106] type 00 class 0x020000
pci 0000:01:04.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:04.0: supports D1 D2
pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:05.0: [1106:3106] type 00 class 0x020000
pci 0000:01:05.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:05.0: supports D1 D2
pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:06.0: [1106:3106] type 00 class 0x020000
pci 0000:01:06.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:06.0: supports D1 D2
pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:07.0: [1106:3106] type 00 class 0x020000
pci 0000:01:07.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:07.0: supports D1 D2
pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3cold
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]
pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]
pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]
pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]
pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18800fff]
pci 0000:00:02.0: BAR 0: assigned [io  0x18801000-0x188010ff]
pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]
pci 0000:00:03.0: BAR 0: assigned [io  0x18801400-0x188014ff]
pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]
pci 0000:01:02.0: BAR 0: assigned [io  0x18800000-0x188000ff]
pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]
pci 0000:01:03.0: BAR 0: assigned [io  0x18800400-0x188004ff]
pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]
pci 0000:01:04.0: BAR 0: assigned [io  0x18800800-0x188008ff]
pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]
pci 0000:01:05.0: BAR 0: assigned [io  0x18800c00-0x18800cff]
pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]
pci 0000:01:06.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:06.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]
pci 0000:01:07.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:07.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]
pci 0000:00:06.0: PCI bridge to [bus 01]
pci 0000:00:06.0:   bridge window [io  0x18800000-0x18800fff]
pci 0000:00:06.0:   bridge window [mem 0x50000000-0x500fffff]


Code: [Select]

via-rhine 0000:00:02.0: enabling device (0080 -> 0083)
via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142
via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:00:03.0: enabling device (0080 -> 0083)
via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143
via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
pci 0000:00:06.0: enabling device (0000 -> 0003)
via-rhine 0000:01:02.0: enabling device (0080 -> 0083)
via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141
via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:03.0: enabling device (0080 -> 0083)
via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143
via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:04.0: enabling device (0080 -> 0083)
via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140
via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:05.0: enabling device (0080 -> 0083)
via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142
via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:06.0: enabling device (0080 -> 0082)
via-rhine 0000:01:06.0: MMIO do not match PIO [06] (1a != ff)
via-rhine: probe of 0000:01:06.0 failed with error -5
via-rhine 0000:01:07.0: enabling device (0080 -> 0082)
via-rhine 0000:01:07.0: MMIO do not match PIO [06] (1a != ff)
ata1.00: CFA: HMS360404D5CF00, DN4OCA2A, max PIO4
ata1.00: 7999488 sectors, multi 0: LBA
via-rhine: probe of 0000:01:07.0 failed with error -5


[DiTBho]

If that causes the last two Ethernet interfaces to fail with ioremap failed, or the two lock up during operation, a (better!) possibility is that the fourth interface per chip can still be used in PIO mode:

Code: [Select]

static int rhine_init_one_pci(struct pci_dev *pdev,
      const struct pci_device_id *ent)
{
struct device *hwdev = &pdev->dev;
int rc;
long pioaddr, memaddr;
void __iomem *ioaddr;
int io_size = pdev->revision < VTunknown0 ? 128 : 256;

/* This driver was written to use PCI memory space. Some early versions
 * of the Rhine may only work correctly with I/O space accesses.
 * TODO: determine for which revisions this is true and assign the flag
 * in code as opposed to this Kconfig option (???)
 */
#ifdef CONFIG_VIA_RHINE_MMIO
u32 quirks = rqNeedEnMMIO;
#else
u32 quirks = 0;
#endif

rc = pci_enable_device(pdev);
if (rc)
goto err_out;

if (pdev->revision < VTunknown0) {
quirks |= rqRhineI;
} else if (pdev->revision >= VT6102) {
quirks |= rqWOL | rqForceReset;
if (pdev->revision < VT6105) {
quirks |= rqStatusWBRace;
} else {
quirks |= rqIntPHY;
if (pdev->revision >= VT6105_B0)
quirks |= rq6patterns;
if (pdev->revision >= VT6105M)
quirks |= rqMgmt;
}
}

        // If MMIO mapping is not possible, use PIO.
        if ((pci_resource_len(pdev, 0) < io_size) ||
    (pci_resource_len(pdev, 1) < io_size))
quirks |= rqNeedEnMMIO;

pioaddr = pci_resource_start(pdev, 0);
memaddr = pci_resource_start(pdev, 1);

pci_set_master(pdev);

rc = pci_request_regions(pdev, DRV_NAME);
if (rc) {
dev_err(hwdev, "Insufficient PCI resources (%d and %d out of %d), aborting\n",
                         pci_resource_len(pdev, 0), pci_resource_len(pdev, 1), io_size);
goto err_out_pci_disable;
        }

ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
if (!ioaddr) {
rc = -EIO;
dev_err(hwdev,
"ioremap failed for device %s, region 0x%X @ 0x%lX\n",
dev_name(hwdev), io_size, memaddr);
goto err_out_free_res;
}

enable_mmio(pioaddr, quirks);

rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
if (rc)
goto err_out_unmap;

rc = rhine_init_one_common(&pdev->dev, quirks,
   pioaddr, ioaddr, pdev->irq);
if (!rc)
return 0;

err_out_unmap:
pci_iounmap(pdev, ioaddr);
err_out_free_res:
pci_release_regions(pdev);
err_out_pci_disable:
pci_disable_device(pdev);
err_out:
return rc;
}

CONFIG_VIA_RHINE_MMIO disabled

Code: [Select]

PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]
pci_bus 0000:00: root bus resource [io  0x18800000-0x188fffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [111d:0000] type 00 class 0x000000
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]
pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
pci 0000:00:02.0: [1106:3106] type 00 class 0x020000
pci 0000:00:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:02.0: supports D1 D2
pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:03.0: [1106:3106] type 00 class 0x020000
pci 0000:00:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:03.0: supports D1 D2
pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000
pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]
pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]
pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]
pci 0000:00:06.0: [3388:0031] type 01 class 0x060400
pci 0000:00:06.0: supports D1 D2
pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hot
pci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci_bus 0000:01: extended config space not accessible
pci 0000:01:02.0: [1106:3106] type 00 class 0x020000
pci 0000:01:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:02.0: supports D1 D2
pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:03.0: [1106:3106] type 00 class 0x020000
pci 0000:01:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:03.0: supports D1 D2
pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:04.0: [1106:3106] type 00 class 0x020000
pci 0000:01:04.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:04.0: supports D1 D2
pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:05.0: [1106:3106] type 00 class 0x020000
pci 0000:01:05.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:05.0: supports D1 D2
pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:06.0: [1106:3106] type 00 class 0x020000
pci 0000:01:06.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:06.0: supports D1 D2
pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:07.0: [1106:3106] type 00 class 0x020000
pci 0000:01:07.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:07.0: supports D1 D2
pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3cold
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]
pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]
pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]
pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]
pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18800fff]
pci 0000:00:02.0: BAR 0: assigned [io  0x18801000-0x188010ff]
pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]
pci 0000:00:03.0: BAR 0: assigned [io  0x18801400-0x188014ff]
pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]
pci 0000:01:02.0: BAR 0: assigned [io  0x18800000-0x188000ff]
pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]
pci 0000:01:03.0: BAR 0: assigned [io  0x18800400-0x188004ff]
pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]
pci 0000:01:04.0: BAR 0: assigned [io  0x18800800-0x188008ff]
pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]
pci 0000:01:05.0: BAR 0: assigned [io  0x18800c00-0x18800cff]
pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]
pci 0000:01:06.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:06.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]
pci 0000:01:07.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:07.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]
pci 0000:00:06.0: PCI bridge to [bus 01]
pci 0000:00:06.0:   bridge window [io  0x18800000-0x18800fff]
pci 0000:00:06.0:   bridge window [mem 0x50000000-0x500fffff]


Code: [Select]

via-rhine 0000:00:02.0: enabling device (0080 -> 0083)
via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142
via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:00:03.0: enabling device (0080 -> 0083)
via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143
via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
pci 0000:00:06.0: enabling device (0000 -> 0003)
via-rhine 0000:01:02.0: enabling device (0080 -> 0083)
via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141
via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:03.0: enabling device (0080 -> 0083)
via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143
via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:04.0: enabling device (0080 -> 0083)
via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140
via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:05.0: enabling device (0080 -> 0083)
via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142
via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:06.0: enabling device (0080 -> 0082)
via-rhine 0000:01:06.0: MMIO do not match PIO [06] (1a != ff)
via-rhine: probe of 0000:01:06.0 failed with error -5
via-rhine 0000:01:07.0: enabling device (0080 -> 0082)
via-rhine 0000:01:07.0: MMIO do not match PIO [06] (1a != ff)


[Nominal Animal]

My suggested rqEnMMIO quirk is invalid, because the bridge ran out of I/O addresses, not memory addresses.

Code: [Select]

pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]
pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18800fff]
pci 0000:00:06.0: PCI bridge to [bus 01]
pci 0000:00:06.0:   bridge window [io  0x18800000-0x18800fff]
pci 0000:00:06.0:   bridge window [mem 0x50000000-0x500fffff]

pci 0000:00:02.0: BAR 0: assigned [io  0x18801000-0x188010ff]
pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]
pci 0000:00:03.0: BAR 0: assigned [io  0x18801400-0x188014ff]
pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]

pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]
pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]
pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]
pci 0000:01:02.0: BAR 0: assigned [io  0x18800000-0x188000ff]
pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]
pci 0000:01:03.0: BAR 0: assigned [io  0x18800400-0x188004ff]
pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]
pci 0000:01:04.0: BAR 0: assigned [io  0x18800800-0x188008ff]
pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]
pci 0000:01:05.0: BAR 0: assigned [io  0x18800c00-0x18800cff]
pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]
pci 0000:01:06.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:06.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]
pci 0000:01:07.0: BAR 0: no space for [io  size 0x0100]
pci 0000:01:07.0: BAR 0: failed to assign [io  size 0x0100]
pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]


The issue is that the bridge I/O address window is only 0x18800000-0x18800fff (4k), but the kernel needs to stuff eight 1k windows into it.  (The I/O address alignment is 0x400 = 1024, i.e. each device will get their own I/O address range aligned to a multiple of 0x400 = 1024.)

The solution would be to increase its I/O window to 8k, so that
    pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18800fff]
becomes
    pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18801fff]
pushing 0000:00:02.0 and 0000:00:03.0 upwards accordingly.  The PCI root has been assigned [io 0x18800000-0x188fffff], so there is plenty of I/O address space left; the kernel just didn't assign enough to the bridge!

There is no physical reason for such a small I/O address range; the bridge will be able to map at least 64k, if not more.  The bug is kernel not accounting enough I/O addresses in the 0000:01 bus.  One reason could be that pci_hotplug_io_size is too small.  Could you check by booting with kernel command line
    hpiosize=8192
to verify?

I'm not absolutely sure if 0000:00:06.0 is a hotplug bridge, so that might not fix the issue.  As a cruder test, you could modify drivers/pci/setup-bus.c:__pci_bus_size_bridges(), in the switch (hdr_type), case PCI_HEADER_TYPE_BRIDGE:, just before the fallthrough;, adding
    additional_io_size += 4096; // Add 4k I/O address space to the bridge
The practical result of this change is that all PCI bridges in your system will reserve an extra 4096 I/O addresses.

Both of these changes should only affect 0000:00:06.0 (plus the I/O address ranges for 0000:00:02.0 and 0000:00:03.0, pushing them higher in the address spaces); seeing the specific change in the I/O mapping would be very informative.  Could you test these?  🤗

[DiTBho]

Code: [Select]

Add 8k I/O address space to the bridge
--- drivers/pci/setup-bus.c.original    2025-02-16 02:41:09.966000000 -0000
+++ drivers/pci/setup-bus.c     2025-02-16 02:41:09.955000000 -0000
@@ -1241,6 +1241,9 @@
                hdr_type = bus->self->hdr_type;
        }

+                        additional_io_size += 4096; // suppa Add 4k I/O address space to the bridge
+                        additional_io_size += 4096; // suppa Add 4k I/O address space to the bridge
+
        switch (hdr_type) {
        case PCI_HEADER_TYPE_CARDBUS:
                /* Don't size CardBuses yet */


Code: [Select]

PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]
pci_bus 0000:00: root bus resource [io  0x18800000-0x188fffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [111d:0000] type 00 class 0x000000
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref]
pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
pci 0000:00:02.0: [1106:3106] type 00 class 0x020000
pci 0000:00:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:02.0: supports D1 D2
pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:03.0: [1106:3106] type 00 class 0x020000
pci 0000:00:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:00:03.0: supports D1 D2
pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:00:04.0: [13a3:0020] type 00 class 0x0b4000
pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x00000fff]
pci 0000:00:04.0: reg 0x14: [mem 0x00000000-0x00001fff]
pci 0000:00:04.0: reg 0x18: [mem 0x00000000-0x00007fff]
pci 0000:00:06.0: [3388:0031] type 01 class 0x060400
pci 0000:00:06.0: supports D1 D2
pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hot
pci 0000:00:06.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci_bus 0000:01: extended config space not accessible
pci 0000:01:02.0: [1106:3106] type 00 class 0x020000
pci 0000:01:02.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:02.0: supports D1 D2
pci 0000:01:02.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:03.0: [1106:3106] type 00 class 0x020000
pci 0000:01:03.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:03.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:03.0: supports D1 D2
pci 0000:01:03.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:04.0: [1106:3106] type 00 class 0x020000
pci 0000:01:04.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:04.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:04.0: supports D1 D2
pci 0000:01:04.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:05.0: [1106:3106] type 00 class 0x020000
pci 0000:01:05.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:05.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:05.0: supports D1 D2
pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:06.0: [1106:3106] type 00 class 0x020000
pci 0000:01:06.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:06.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:06.0: supports D1 D2
pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:07.0: [1106:3106] type 00 class 0x020000
pci 0000:01:07.0: reg 0x10: [io  0x0000-0x00ff]
pci 0000:01:07.0: reg 0x14: [mem 0x00000000-0x000000ff]
pci 0000:01:07.0: supports D1 D2
pci 0000:01:07.0: PME# supported from D1 D2 D3hot D3cold
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:06.0: BAR 8: assigned [mem 0x50000000-0x500fffff]
pci 0000:00:04.0: BAR 2: assigned [mem 0x50100000-0x50107fff]
pci 0000:00:04.0: BAR 1: assigned [mem 0x50108000-0x50109fff]
pci 0000:00:04.0: BAR 0: assigned [mem 0x5010a000-0x5010afff]
pci 0000:00:06.0: BAR 7: assigned [io  0x18800000-0x18801fff]
pci 0000:00:02.0: BAR 0: assigned [io  0x18802000-0x188020ff]
pci 0000:00:02.0: BAR 1: assigned [mem 0x5010b000-0x5010b0ff]
pci 0000:00:03.0: BAR 0: assigned [io  0x18802400-0x188024ff]
pci 0000:00:03.0: BAR 1: assigned [mem 0x5010b100-0x5010b1ff]
pci 0000:01:02.0: BAR 0: assigned [io  0x18800000-0x188000ff]
pci 0000:01:02.0: BAR 1: assigned [mem 0x50000000-0x500000ff]
pci 0000:01:03.0: BAR 0: assigned [io  0x18800400-0x188004ff]
pci 0000:01:03.0: BAR 1: assigned [mem 0x50000100-0x500001ff]
pci 0000:01:04.0: BAR 0: assigned [io  0x18800800-0x188008ff]
pci 0000:01:04.0: BAR 1: assigned [mem 0x50000200-0x500002ff]
pci 0000:01:05.0: BAR 0: assigned [io  0x18800c00-0x18800cff]
pci 0000:01:05.0: BAR 1: assigned [mem 0x50000300-0x500003ff]
pci 0000:01:06.0: BAR 0: assigned [io  0x18801000-0x188010ff]
pci 0000:01:06.0: BAR 1: assigned [mem 0x50000400-0x500004ff]
pci 0000:01:07.0: BAR 0: assigned [io  0x18801400-0x188014ff]
pci 0000:01:07.0: BAR 1: assigned [mem 0x50000500-0x500005ff]
pci 0000:00:06.0: PCI bridge to [bus 01]
pci 0000:00:06.0:   bridge window [io  0x18800000-0x18801fff]
pci 0000:00:06.0:   bridge window [mem 0x50000000-0x500fffff]


Code: [Select]

via-rhine 0000:00:02.0: enabling device (0080 -> 0083)
via-rhine 0000:00:02.0 eth1: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1c, IRQ 142
via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:00:03.0: enabling device (0080 -> 0083)
via-rhine 0000:00:03.0 eth2: VIA Rhine III at (ptrval), 00:0c:42:0e:9f:1d, IRQ 143
via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
pci 0000:00:06.0: enabling device (0000 -> 0003)
via-rhine 0000:01:02.0: enabling device (0080 -> 0083)
via-rhine 0000:01:02.0 eth3: VIA Rhine III at (ptrval), 00:0c:42:03:58:fb, IRQ 141
via-rhine 0000:01:02.0 eth3: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:03.0: enabling device (0080 -> 0083)
via-rhine 0000:01:03.0 eth4: VIA Rhine III at (ptrval), 00:0c:42:03:58:fc, IRQ 143
via-rhine 0000:01:03.0 eth4: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:04.0: enabling device (0080 -> 0083)
via-rhine 0000:01:04.0 eth5: VIA Rhine III at (ptrval), 00:0c:42:03:58:fd, IRQ 140
via-rhine 0000:01:04.0 eth5: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:05.0: enabling device (0080 -> 0083)
via-rhine 0000:01:05.0 eth6: VIA Rhine III at (ptrval), 00:0c:42:03:58:fe, IRQ 142
via-rhine 0000:01:05.0 eth6: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:06.0: enabling device (0080 -> 0083)
via-rhine 0000:01:06.0 eth7: VIA Rhine III at (ptrval), 00:0c:42:03:58:ff, IRQ 141
via-rhine 0000:01:06.0 eth7: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000
via-rhine 0000:01:07.0: enabling device (0080 -> 0083)
via-rhine 0000:01:07.0 eth8: VIA Rhine III at (ptrval), 00:0c:42:03:59:00, IRQ 143
via-rhine 0000:01:07.0 eth8: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000


Code: [Select]

rb532 / # ifconfig -a
eth0      Link encap:Ethernet  HWaddr 00:0c:42:0e:9f:1b
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:40

eth1      Link encap:Ethernet  HWaddr 00:0c:42:0e:9f:1c
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth2      Link encap:Ethernet  HWaddr 00:0c:42:0e:9f:1d
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth3      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fb
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth4      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fc
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth5      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fd
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth6      Link encap:Ethernet  HWaddr 00:0c:42:03:58:fe
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth7      Link encap:Ethernet  HWaddr 00:0c:42:03:58:ff
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth8      Link encap:Ethernet  HWaddr 00:0c:42:03:59:00
          BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

lo        Link encap:Local Loopback
          LOOPBACK  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)


Code: [Select]

cat .config | grep HOTPLUG_PCI
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set


Code: [Select]

rb532a # cat /proc/cmdline
console=ttyS0,9600 gpio=16383 mem=64M init=/bin/bash rootfstype=xfs ro acpi=off hpiosize=8192

Note that the modified lines are a bit different from what you suggested.
This way it works.

It still seems like something is wrong

Code: [Select]

        /* The root bus? */
        if (pci_is_root_bus(bus)) {
                host = to_pci_host_bridge(bus->bridge);
                if (!host->size_windows)
                        return;
                pci_bus_for_each_resource(bus, pref, i)
                        if (pref && (pref->flags & IORESOURCE_PREFETCH))
                                break;
                hdr_type = -1;  /* Intentionally invalid - not a PCI device. */
        } else {
                pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
                hdr_type = bus->self->hdr_type;
        }

                        additional_io_size += 4096; // suppa Add 4k I/O address space to the bridge
                        additional_io_size += 4096; // suppa Add 4k I/O address space to the bridge

        switch (hdr_type) {
        case PCI_HEADER_TYPE_CARDBUS:
                /* Don't size CardBuses yet */
                break;

        case PCI_HEADER_TYPE_BRIDGE:
                pci_bridge_check_ranges(bus);
                if (bus->self->is_hotplug_bridge) {
                        additional_io_size  = pci_hotplug_io_size;
                        additional_mmio_size = pci_hotplug_mmio_size;
                        additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
                }
                fallthrough;