In your simulation, you should also display your 3 bit counter's output so you may see if it is counting properly. This will help you debug.
If you are designing to eventually place this logic in a PLD:
I'm curious. You appear to be using an old quartus schematic entry, manually entering gates and wires.
Would you not prefer to do this in an HDL language like verilog or System Verilog?
It would be much easier to code, simulate and edit as you are talking about a basic setup, then very few lines of code.
Also, you may use a proper simulator like Modelsim which is also available for free with Quartus as well as for most other FPGA vendors.