FPGA

FPGA VGA Controller for 8-bit computer

« 1 2 3 4 5 6 ... 53 »

New FPGA manufacturer - German Cologne Chip

Home made SystemVerilog 3 word, Zero latency FIFO, documented for beginners.

« 1 2  All »

Learning how to deal with FPGAs

CRC circuit

Programming device for MACHXO2?

Open source FPU with 1 cycle performance

« 1 2  All »

Net 'myled' does not have a driver?

2nd Order Sigma-Delta Digital to Analogue Converter (SD-DAC) in Verilog

« 1 2  All »

Power Consumption of Cyclone IV on each voltage rail

Cyclone 5 recovered from scrap boards

SQRL Acorn as an interesting Artix-7 board?

« 1 2 3  All »

Xilinx ISE - how to improve erratic timing optimization?

« 1 2 3  All »

How do I write VHDL that can keep up with a 6.6Gb/s GTP?

Programming CPLD

Spartan-6 DCM_CLKGEN -- unexpected derived timing constraints

Atmel ATF150x CPLD and WinCUPL

FPGA ide, currently using quartis 2

Quartus M10K ModelSim fails

Picking a "core frequency" for a FPGA

« 1 2  All »

Can anyone program a PLS153 or a 82S153 from a good part/

Gowin Simulation

Getting a Verilog PS/2 interface working

« 1 2  All »

Altera configuration Flash - crazy prices - alternatives?

Using code to remove bounce

Tasks in Verilog on Clock edges

Spartan-6 CCLK switching to 50 MHz -- why?!

Counting in state-machines

How to hack the EP1K30TC144-3N ?

ADC with Altera Cyclone FPGA - internal and external (I2C) implementation

« 1 2  All »

WTF Xilinx

« 1 2 3 4 5  All »

Creating a simple testbench

Programming ICE40 FPGA on a board?

Custom Spartan-7 FPGA board for beginners

« 1 2  All »

Your choice for <$3 FPGA/CPLD with >50 IO, >200 LUT4?

How often do new series of FPGAs come out (xilinx)

Developer runs Doom on Altera CycloneV

TL866CS on Linux/ WINE

What are CPLDs, do they still play a role, how to program them?

FPGA SD controller issues - Cross Domain Clock issue?