Vivado 2026.1 is out

[hamster_nz]

Who's keen to try it?

Would like some feedback on the new licensing co-existing with earlier releases before I take the plunge.

It would allow me to target my Kintex-7 board which sits idle since I upgraded PCs and lost my node-locked license.

Edit: Taking the plunge and installing on my home laptop... will report back.

[hamster_nz]

Obtaining the licensing was how I remember it (painful, but not too painful if you have done it once before).

Can now target Kintex 7 parts - so that's a win.

Code: [Select]

Starting synth_design
Attempting to get a license for feature 'Vivado_Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Vivado_Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Designutils 20-5008] Incremental synthesis strategy default
....
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 3510.332 ; gain = 327.020 ; free physical = 1169 ; free virtual = 13455


[asmi]

Who's keen to try it?

Would like some feedback on the new licensing co-existing with earlier releases before I take the plunge.

I'm going to stay on 2025.2, limitations of the new license are too severe, not to mention forced renewals make me very suspicious of their real motives down the line. One person on their forums already tried simulation, and design taking about 30% of A200T was too large for simulation. So screw that! It wouldn't be the first good tool killed by greed.

It would allow me to target my Kintex-7 board which sits idle since I upgraded PCs and lost my node-locked license.

If you know the NIC ID for that license (you can normally find it on their self-licensing portal), you can always assign it to your new network card and the license will work just fine. Already did this twice with my K325T license I got with Genesys 2 board many years ago.

[asmi]

Also - beware that from July 1st, if you activate a license voucher which comes with a devboard, you only get a one year rental license instead of a permanent one like it was before, and after a year you will have to pay up, or throw the devboard away because your license will turn into a pumpkin. So they now want you to pay for the right to use your own damn hardware. Which kind of means you don't really own it anymore...

[Unixon]

Who's keen to try it?

Last version available on the turbulent streams is Vitis Core Development Kit 2025.2 and it is 102Gb compressed.
However, it is not very useful for those who can't own those top level FPGAs 

[glenenglish]

I am also staying on Vivado 2025.2 and Vitis 2024 (classic mode)

AMD have completely hobbled the basic tool. The simulator has lost its excellent multithreaed performance and other capabilities, the multicore P&R is hobbled,  and only one ILA permitted WTF ? how to debug something with different clocks ? I have  told AMD and the local FAEs exactly what i think of this and it isnt nice.

This is now a fork in the road for me - going to Altera AGilex.
I was about too start work with SU45/ SU65  devices- well priced, pretty good really, but need 2026 . 

So, I need to decide to spend USD$5500 on the perpetual enterprise license  and put a hole in my cash flow (which is already hurting because I have needed to buy enough  parts to be 2 years ahead )

Or I go to Altera , and their tools are free for all Agilex 3 and Agilex5E devices  and that gets you some pretty high end horsepower. and they're competitively priced. Agilex parts have some greatt features for the money (modern DSP blocks and 10 gig ethernet and A76 cortex APU)  and they seem to be fixing up their documentation, thank god.
I think the IP cost issue is solved- if you go cap in hand they'll likely give you the BaseIP for free, and for most of us , the BaseIP is where the work is, and if you need something exotic, then you can make the choice of write it yourself or buy a perpetual for that IP.

Efinix is another option but it means I will need to drop 10-15k on a mixed language simulator (probably ALDEC). I let my old single language sim license on Modelsim lapse once Xilinx XSIM was runnign rings around modelsim in sim time !

[asmi]

Or I go to Altera , and their tools are free for all Agilex 3 and Agilex5E devices  and that gets you some pretty high end horsepower. and they're competitively priced. Agilex parts have some greatt features for the money (modern DSP blocks and 10 gig ethernet and A76 cortex APU)  and they seem to be fixing up their documentation, thank god.

Do you have any specific recommendations for a devboards with good price/value ratio?
Also - are they still placing SDRAM chips onto their devboards because they don't want to give out DDR controller IPs? I mean - c'mon, it's not 1990's anymore! How can you seriously do just about anything with that kind of memory? I have a bunch of projects which hardly fit into bandwidth provided by 64 bit@400 MHz DDR3 interface - which is why I had to shoehorn a 64bit SODIMM-DD3 interface into A100-484 device by (ab-)using configuration banks for the memory interface, and then using level shifters to actually have a qspi flash device for it to boot up from.

I think the IP cost issue is solved- if you go cap in hand they'll likely give you the BaseIP for free, and for most of us , the BaseIP is where the work is, and if you need something exotic, then you can make the choice of write it yourself or buy a perpetual for that IP.

Not sure I understood this right. Do they still require paid subscription to get access to those IPs? It's been a while since I looked at them. Great IP library available for free was a big selling point for me in Xilinx camp.

Efinix is another option but it means I will need to drop 10-15k on a mixed language simulator (probably ALDEC). I let my old single language sim license on Modelsim lapse once Xilinx XSIM was runnign rings around modelsim in sim time !

I was looking at Efinix, but lack of simulator was a big put-off for me. Good simulator was among the things which lead me into Xilinx camp to begin with. With Altera you realistically will need to at least buy upgraded sim license as the one included is very crippled.
I decided for myself that I will stay in the 2025.2.1 version unless there will ever be a business case for buying a perpetual enterprise license, but until and unless that happens, I will look elsewhere for new stuff. Most of my existing projects are using older "established" devices which are covered by 2025.2.1, so it's not really an issue. It sucks that I can't take a look at newer SU+ devices as I was really looking forward to trying those because they do look promising on paper, but not at the price AMD wants me to pay.

[glenenglish]

Hi Asmi
(1)
I would stick to the manufacturer's dev boards for the moment, no doubt Digilient will come out with something.
I have ordered a : https://www.altera.com/products/devkit/po-3196/agilex-5-fpga-e-series-013b-development-kit
there is also a similar for A3C in same form :
https://www.altera.com/products/devkit/po-3000/agilex-3-fpga-and-soc-c-series-development-kit

make sure anythign you buy if used isnt the engineering silicon version. And for those boards, there is a PCI card adaptor so you can plug it into a PC and exercise the PCIexpress caps.
These are the lowest end vendor's dev boards , but appear to be fully supported for  examples.
They've got LPDDR4 on them

(2) IP - yeah Altera in the catalog, the Base IP is 6k ( FIR, FFT etc) .   If you make a case that you are jumping from Xilinx to become an Altera shop, they might waive this for you as a single developer.  Your mileage may vary. There is ALOT of pain moving from Xilinx to Altera and that I think can justify getting this free since I will be the one with pain.

Now I am not so fussed now i think about IP, given how many high level tools there are now of different ilks, as I can write the cores. There are many high level tools to make the HDL for you with agents doing the code work fro your spinal HDL, pythonhdl etc,
However !  is that when you use the IP cores, vendor's IP cores are highly optimized for their architecture.
example : If implementing a FIR at say 300 MHz, with 300 Msps sample rate,  you dont have ANY room to waste a clock cycle, so you really have to know what you're doing... Wasteing a clock cycle could mean a 2:1 increase in DSP block usage... and all the extra timing and route issues that might go with that ,,,,

I think the embedded tools in ALtera QPP Agilex are sooo much nicer than the nightmare that VITIS is..... They got a separate company to do it in a closed package. It is easy and uncomplicated. Vitis sure you can do anythign on the planet and the complexity is clear but most of us dont need 90% of that.

(3) Xilinx now with the 5.5k perpetual license cost (but you get everything) is the new world it seems.
5.5k for perpetual enterprise seems like a pretty good deal I think- But Xilinx dont have the devices I want anymore. They're obsessed with the Military RADAR and AI datacentre accelerator revenue.
Even if Xilinx did me a deal, I am not sure that I would stay with Xilinx. Xilinx have done nothign new IMO in the mid range, and ALtera (now)  have the best mid range options ever in the industry, i think, from small parts  (A3C025) to large devices in Agilex 5E and D. and their devices have modern features (DSPs with FPU, tensor).

I was goign to try and stick it out with Xilinx but the licensing change has given me 2nd thoughts. And as other's have written, where are the new Zynqs   the cheapest you can get a MPSoC ZU1 part asking nicely is still MORE THAN DOUBLE  the street price of a Z7010 !!  I am hooked on  SoC , the hard , fast processor buys you 10x the number of DMIPS compared to a soft processor, and that frankly, buys alot of software time that you dont need to optimize ! My backup was to try and get a rock bottom price on a ZU1 to replace my Zynq designs.

(4) EFINIX.
yeah. LUT4, interesting fabric etc, interconnect  seems to work OK.  (BTW not all interconnect is through XLRs, there is some localized private routing in groups - see the patent) -- you need to place an extra pipelining stage in there if you want to cross the chip , however I think , excellent stuff. the tools seem to work and now they have recently introduced  partitioned designs - this is new and exciting.  and they fixed the interface designer BS so now you instantiate IO ports in your HDL not separate GUIs.
The thing I have found is,  Efinix is not all that cost effective unless you are buying lots of trays, they have a fairly steep and seemingly inflexible pricing strategy. The fabric etc is all fast  but it needs to be with their interconnect arch. The DSPs will run at 1000 MHz, but they dont have much in extra features (which I guess makes them fast) . They can do BLOAT16 MUL ACC = FP32 though.....
I like the simplicity of the tools. Their hard and soft SoC is excellent . The SOFT RV64  IP is faster in the real world than their RV32 soft soc with all the branch predictors etc  and what I would recommend.
of course, support , well if you need it you need the FAE who knows someone at the factory.  They do seem to take notice of bugs and fix them. even if they seem a bit non responsive in the forums
Yes, you need to buy a simulator..... the Quartus Prime Pro built in sim is pretty well equiv to the xilinx I think . so far.....


SU+ is well priced, the packages are a bit annoying for me  - 400 ball 0.5mm , or 600 ball 0.8     no like 300 ball 0.8mm package like 7 series., but ultrascale+ is still fast, and the tools and the routing work well, US+ in all variants is an absolute pleasure to work with...... I consider running a 64 bit fully optioned microblaze instead of going the SoC way.  But, turns out, Xilinx in SU+  is only supporting LPDDR4X and LPDDR5 (lower VIO) but with all these memory issues, I really just want to stick to using what I have trays of - ECC LPDDR4.....  (I use built in ECC LPDDR4 for all my work) .  And, since I have been using hard controllers, I cannot be arsed anymore with the hassles of trying to run soft fabric memory controllers fast..

I've also been dabbling in on FPGA fixed burned in LLMs / transformers- where you want LOTS of hard muls and LUT-ROMs( hard weights synthesised into the fabric) . Efinix might be a good solution for the simply, mass fabric requirement there without giant wide data  lanes...  Efinix with their new 12nm devices, they've been announced for a year but nothign has happened so far.... but they go to 127 Mbits of block ram.....
The efinix advantage is- no money out of tools and IP,  (although I would argue that USD 5k on tools once for perpetual isnt a big impost if I play the long game)
but, with Efinix i think that you very much are on your own with just a solid set of build tools.  Price wise...  Yes you can get more transceivers  and useful high speed IOs per $ than Agilex and Xilinx. but in most cases what Agilex and Xilinx give you is sufficient.

Xilinx have trashed their low end student market with the license change, the hobbling of the BASIC tool is just a F___ing joke.  Useless debugger, sim, tools....   I am prepared to say "Good riddance" with that. But, Altera is a bit unknown now, just what their longevity is, and the continuously moving  understanding of exactly how the tools are licensed- even the local FAE doesnt really understand it .  I still dont fully understand their renew etc model, no one seems to, make sure you get that in writing from your FAE so you can wave it around if you have trouble.....
hence the Efinix play....
-glen

[asmi]

Hi Asmi
(1)
I would stick to the manufacturer's dev boards for the moment, no doubt Digilient will come out with something.
I have ordered a : https://www.altera.com/products/devkit/po-3196/agilex-5-fpga-e-series-013b-development-kit
there is also a similar for A3C in same form :
https://www.altera.com/products/devkit/po-3000/agilex-3-fpga-and-soc-c-series-development-kit

make sure anythign you buy if used isnt the engineering silicon version. And for those boards, there is a PCI card adaptor so you can plug it into a PC and exercise the PCIexpress caps.
These are the lowest end vendor's dev boards , but appear to be fully supported for  examples.
They've got LPDDR4 on them

Wow, these are quite pricey.

(2) IP - yeah Altera in the catalog, the Base IP is 6k ( FIR, FFT etc) .   If you make a case that you are jumping from Xilinx to become an Altera shop, they might waive this for you as a single developer.  Your mileage may vary. There is ALOT of pain moving from Xilinx to Altera and that I think can justify getting this free since I will be the one with pain.

Now I am not so fussed now i think about IP, given how many high level tools there are now of different ilks, as I can write the cores. There are many high level tools to make the HDL for you with agents doing the code work fro your spinal HDL, pythonhdl etc,
However !  is that when you use the IP cores, vendor's IP cores are highly optimized for their architecture.
example : If implementing a FIR at say 300 MHz, with 300 Msps sample rate,  you dont have ANY room to waste a clock cycle, so you really have to know what you're doing... Wasteing a clock cycle could mean a 2:1 increase in DSP block usage... and all the extra timing and route issues that might go with that ,,,,

What I want to know is if I buy a full license, will it turn into a pumpkin in a year, or I will be able to use the then-current version for as long as I wish (kind of like Xilinx devkits before current trashing it down). If it's the latter, then buying a license once would make sense and it's not that big of a deal - but again provided that there will be a business case for it, because spending that kind of money on a hobby is way beyond affordability for me.

I think the embedded tools in ALtera QPP Agilex are sooo much nicer than the nightmare that VITIS is..... They got a separate company to do it in a closed package. It is easy and uncomplicated. Vitis sure you can do anythign on the planet and the complexity is clear but most of us dont need 90% of that.

I disagree. For all the clunkiness of Vitis I will take VS code over Eclipse every day, besides, Vitis in 2025.2 is in pretty decent shape. The only thing that really drives me nuts in VS code is it's very rudimentary debugging functionality - for example I still don't know if it's possible to have some variables displayed in base10, while some other is base16.

(3) Xilinx now with the 5.5k perpetual license cost (but you get everything) is the new world it seems.
5.5k for perpetual enterprise seems like a pretty good deal I think- But Xilinx dont have the devices I want anymore. They're obsessed with the Military RADAR and AI datacentre accelerator revenue.
Even if Xilinx did me a deal, I am not sure that I would stay with Xilinx. Xilinx have done nothign new IMO in the mid range, and ALtera (now)  have the best mid range options ever in the industry, i think, from small parts  (A3C025) to large devices in Agilex 5E and D. and their devices have modern features (DSPs with FPU, tensor).

It's not a bad thing if the payment is a one-time thing, not ongoing sub which needs to be maintained lest it turns into useless drive space eater.

I was goign to try and stick it out with Xilinx but the licensing change has given me 2nd thoughts. And as other's have written, where are the new Zynqs   the cheapest you can get a MPSoC ZU1 part asking nicely is still MORE THAN DOUBLE  the street price of a Z7010 !!  I am hooked on  SoC , the hard , fast processor buys you 10x the number of DMIPS compared to a soft processor, and that frankly, buys alot of software time that you dont need to optimize ! My backup was to try and get a rock bottom price on a ZU1 to replace my Zynq designs.

Zynqs are good, and particularly because you can actually write a bare-metal code for it, as opposed to being limited to running Linux, which is a requirement for just about any other SoC.

(4) EFINIX.
yeah. LUT4, interesting fabric etc, interconnect  seems to work OK.  (BTW not all interconnect is through XLRs, there is some localized private routing in groups - see the patent) -- you need to place an extra pipelining stage in there if you want to cross the chip , however I think , excellent stuff. the tools seem to work and now they have recently introduced  partitioned designs - this is new and exciting.  and they fixed the interface designer BS so now you instantiate IO ports in your HDL not separate GUIs.
The thing I have found is,  Efinix is not all that cost effective unless you are buying lots of trays, they have a fairly steep and seemingly inflexible pricing strategy. The fabric etc is all fast  but it needs to be with their interconnect arch. The DSPs will run at 1000 MHz, but they dont have much in extra features (which I guess makes them fast) . They can do BLOAT16 MUL ACC = FP32 though.....
I like the simplicity of the tools. Their hard and soft SoC is excellent . The SOFT RV64  IP is faster in the real world than their RV32 soft soc with all the branch predictors etc  and what I would recommend.
of course, support , well if you need it you need the FAE who knows someone at the factory.  They do seem to take notice of bugs and fix them. even if they seem a bit non responsive in the forums
Yes, you need to buy a simulator..... the Quartus Prime Pro built in sim is pretty well equiv to the xilinx I think . so far.....

Their hard RV SoC are interesting, but they are not cheap, and a requirement to "bring your own sim" turns Efinix from free to very expensive and most likely subscription-based ordeal (as sims are mostly subscription-based), which kind of flips the table, and Xilinx no longer seems like joke.

SU+ is well priced, the packages are a bit annoying for me  - 400 ball 0.5mm , or 600 ball 0.8     no like 300 ball 0.8mm package like 7 series., but ultrascale+ is still fast, and the tools and the routing work well, US+ in all variants is an absolute pleasure to work with...... I consider running a 64 bit fully optioned microblaze instead of going the SoC way.  But, turns out, Xilinx in SU+  is only supporting LPDDR4X and LPDDR5 (lower VIO) but with all these memory issues, I really just want to stick to using what I have trays of - ECC LPDDR4.....  (I use built in ECC LPDDR4 for all my work) .  And, since I have been using hard controllers, I cannot be arsed anymore with the hassles of trying to run soft fabric memory controllers fast..

To each their own I guess. I like flexibility provided by soft controllers as you can tailor memory subsystem to the needs of a specific project, while in case of HW blocks you don't really have much of a choice. Besides Atrix US+ can run DDR4 at 1.2 GHz via soft controller, which is not bad, and yet still preserves flexibility to tailot memory system to needs of a specific design.

Xilinx have trashed their low end student market with the license change, the hobbling of the BASIC tool is just a F___ing joke.  Useless debugger, sim, tools....   I am prepared to say "Good riddance" with that. But, Altera is a bit unknown now, just what their longevity is, and the continuously moving  understanding of exactly how the tools are licensed- even the local FAE doesnt really understand it .  I still dont fully understand their renew etc model, no one seems to, make sure you get that in writing from your FAE so you can wave it around if you have trouble.....
hence the Efinix play....
-glen

As much as I agree that AMD turned their free version from useable, but limited product, into a crippled mess which is no good for just about anything, Altera's counterpart seems to be cut down even worse, and there are multiple products which ytou need to license, which brings total $$$ even higher.
---------
Another interesting alternative I'm looking at is a combination of PIC64GX1000 SoC + FPGA. PIC64GX1000 is a 600 MHz 4+1 core RV64 SoC with not much else, but with 1 or 4 lane PCIE interface, which is what I'm thinking of using to connect FPGA part. It can run Linux, and they also promised to support bare-metal development. I have a devboard with that SoC (without FPGA part), and they vendor provides a step-by-step guide on how to do a live debugging of a bare-metal application, and bare-metal drivers for peripherals (including PCIE). Unlike many other SoCs, this one has PCIE without much else, so it's fairly simple and cheap, which is why it looks quite attractive as a pair to FPGA. Right now only part with PCIE x1 is available, with PCIE x4 ipart s now expected to arrive some time next year, and they also have more powerful RV64 SoCs in the pipeline.

[Unixon]

AMD have completely hobbled the basic tool.

Have they done this to 2026.1 release only of should we skip a number of previous releases due to these decisions?

[glenenglish]

"Have they done this to 2026.1 release only of should we skip a number of previous releases due to these decisions?"

no, all is normal up to 2026.

[glenenglish]

Hi Asmi
$1000 from my PRO POV is not too bad for a fully fetaured dev kit. I tell people to buy factory dev hits if they are pros because fif you have some really serious problematic  issue, the factory is going to ask you to set it up for their dev kit so they can take a look for themselves.
There are some others in the few hundred dollar bracket appearing for A3C

I am getting eventually to the bottom of the Altera license thing.   But for sure- the QPP TOOLS A3C and A5E are free forever,  but you do have to take out a license every year  (to get the new version) so they understand who has what and this way they can estimate changes, effects on users.   I am encouraging them to drop their base IP +CIC cost, they should just give that away. NIOS and basic stuff is included in QPP.

I dont like debugging in VS code, it doesnt seem close enough to the metal.

Yes, Zynq and MPSoC I run FreeRTOS+TCP.  I dont have any production builds with Linux on either.  I would love to have a good excuse to to run the Hypervisor on the MPSoC.

Efinix hard SoC. yeah  they really just are not price competitive.  Others have told me they look good, but Xilinx or Altera will do much better in formal sales channels. Efinix dont do any haggling.

You can get a AUP part to run 1.2 GHz DDR4 clock across different builds ? Others i have discussed this with run that as a precompiled (partial reconfig) tile that is a known routing.   And always used manual placement to make it work.
------
Microchip. what happend to  PF2 ? (Polarfire 2 ) Maybe it is time nice to revisit Microchip Polarfire. But Polarfire fabric is old .  Putting aside the RV64, everything about their FPGA fabric is old old old.  The DSP block is like someting out of Spartan 3...LOL  ROFL ...except that if you want a low power platform, it is probably the best shot.  I have a good contact deep in Miicrochip. I will find out WTF? with PF2.

--- which brings me back to Efinix.  The Aldec dual language sim is perpetual.  Efinix for my applications has the best all round feature set.
But, I would tend to buy one device and use it across all products, overkill for some.  Maybe two devices.  That's to get the number of trays up to something where I get a decent price break. There doesnt appear to be any concept of a relationship with the  vendor. That counts for alot for aplayer like me.

back to the problem. do I get a perpetual Xilinx all I can eat, and tough it out with the  Xilinx and their lack of a modern SoC, or the sake of my experience and close relationship with them (and squeeze the vendor on price of the lowest MPSoC ) .

I wont buy from a vendor that wont offer a perpetual, or at least a license that does not stop working. So that I have to get to the bottom of with Altera...glen

[glenenglish]

There is a low cost board for A3C and A5
but they are not SoC versions....
$170

https://www.altera.com/asap/offering/po-3160/de23-lite-development-and-education-board

it has an A3CZ135BB18AE7S   which is a  non SoC part.

There is this one coming soon :
https://www.altera.com/asap/offering/po-3139/atum-a3-nano
it also has a    A3CZ135BB18AE7S

alas both those boards do NOT have the SoC - they are Z siffice. you want W suffix or U suffx

[Unixon]

"Have they done this to 2026.1 release only of should we skip a number of previous releases due to these decisions?"
no, all is normal up to 2026.

OK, thanks, this may save another 105.84Gb of space

[glenenglish]

the thing is, if you want to use the new SU+ parts, you got to run 2026.  In 2025.x, they were still fixing stuff in the tools for SU+

[Unixon]

no, all is normal up to 2026.

I saw release sizes exploded after 2019. What have they included in there that takes up so much space?

[Unixon]

the thing is, if you want to use the new SU+ parts, you got to run 2026.  In 2025.x, they were still fixing stuff in the tools for SU+

Is my estimate right that the bare cost of these parts alone is hmm... uncomfortable?

[glenenglish]

Asmi,

it seems in the fine print, that Xilinx Perpetual just means your software doesnt stop working.  you still got to fork out $$$$ per year to get upgrades. The agent  is not sure.
so, unless I can come to some sort of deal, and I cannot get the deal I want from Altera, that'll probably end my relationship with XIlinx for new projects.

One thing to consider, if the big two are going this way, as a professional developer, I might have to just suck it up.

If Altera keep free tools for A3C and A5E, (with only the paperwork license renewal yearly) I may go that way. I can write my own IP in the high level tools. IE I think you can get a free base IP toolchest coming from Xilinx, but whether they carry that on every year? probably not. 

So, might be a matter of talking to the Efinix agent about getting some staggered delivery long term deals to improve pricing (by some longer term quantity committment) , and buy the ALdec sim.

[glenenglish]

Unixon :
Xilinx SU+ parts are well and competitively priced to any other options you might have.  (except Gowin)

[asmi]

You can get a AUP part to run 1.2 GHz DDR4 clock across different builds ? Others i have discussed this with run that as a precompiled (partial reconfig) tile that is a known routing.   And always used manual placement to make it work.

I don't remember having much issues getting this to work. You have to make sure you have the right package (only FFVB676 and SFVB784 will work) and speed grade (-2 is required), but I never had to use manual placement to get it to work.

Microchip. what happend to  PF2 ? (Polarfire 2 ) Maybe it is time nice to revisit Microchip Polarfire. But Polarfire fabric is old .  Putting aside the RV64, everything about their FPGA fabric is old old old.  The DSP block is like someting out of Spartan 3...LOL  ROFL ...except that if you want a low power platform, it is probably the best shot.  I have a good contact deep in Miicrochip. I will find out WTF? with PF2.

I was talking about their hard SoC, which don't have any fabric, which is why they are relatively cheap (~30$ in qty 25). They are quite barebones as far as typical hard SoCs go, but that's why I like them.

I wont buy from a vendor that wont offer a perpetual, or at least a license that does not stop working. So that I have to get to the bottom of with Altera...glen

Yeah, that's why AMD's decision to stop providing perpetual licenses with devboards is so infuriating, because you basically only rent a devkit instead of buying it unless you happen to have a perpetual license already. And that's what I need to know about Altera's licensing model - if they also follow rental model, I won't touch them with a 10 ft pole.

[asmi]

Asmi,

it seems in the fine print, that Xilinx Perpetual just means your software doesnt stop working.  you still got to fork out $$$$ per year to get upgrades.

Yes that's how Xilinx perpetual licenses work. You can use the version you licensed (that usually means +2 versions from the version which was current at the time of purchase, because purchase includes one year of free updates) forever, but if you want to upgrade, you will have to pay for a new license. And that's fine by me - I don't mind paying for updates as long as I can still continue using the version I paid for forever if I don't want or need to update.

[Unixon]

BTW, are there any estimates what would it cost to buy out exclusive rights for Vivado and other FPGA design software from AMD?
What would it cost to buy out all hardware IP rights?

[ixfd64]

I'm doing some machine learning projects for graduate school and happened to get started with FPGAs today. I just finished setting up Vivado 2026.1 and am using it to build a sample project to test my new Arty A7-100T board.

[glenenglish]

that's a good case for using 2025 (ARTY 7-series board). no reason at all to go 2026
all you will get with 2026 is a hobbled debugger, hobbled simulator etc

I put the the rep that I would be OK with $2k (new/renewal) for PRO (all devices) IF it was perpetual....

After 35 years using ALtium, I changed to Cadence because of Altium's change in licensing.....

[glenenglish]

Hi Asmi
For my applications advantages of the SoC  (combined  process/fpga )  that big wide multiiple bus structure,  there is like 500 Gbps bandwidth between the PS and PL in MPSoC, and about 150Gbps in Zynq, at least. And that's low latency...
- With say PCIgen4 x 4 between devices, that could get you  62 Gbps....  WHich is probably enough, because it would be unusual I think to handle more than that in the PS !

The there is the low latency PL GPIO :
The PS-MIO in EMIO mode  can do its GPIO thing in the PL in a few cycles . Using AXIO GPIO of course can take days to toggle a bit on the other side.
- I cant see how I can replicate that behaviour with the dual device optiion.
- UNless these RV64 devices you speak of have some memory mapped IO pins. , I would want at least 30 to be low latency, or some sort of synchronous bus interconnect between the FPGA

Ha ! I thought about this problem abotu 10 years ago before using Zynq...