VHDL SPI core

[ali_asadzadeh]

Hi,
It seems an obvious code,but
I'm trying to interface the ADS131E08 to my Spartan6 FPGA, the problem is that when I implement my SPI bus, I can access some registers but when I try to verify the written registers some would fail, I want to know if you happen to know a good known source for a Master SPI code in VHDL that would support different modes of CPOL and CPHA modes.

I have tried the FPGA4fun core and my own implementation, but both of them are not working in here.

[DC1MC]

You can try this one:

https://opencores.org/projects/spi_master_slave

 Cheers,
 DC1MC

[ali_asadzadeh]

You can try this one:

https://opencores.org/projects/spi_master_slave

 Cheers,
 DC1MC

Thanks,I have already tried this one too, the problem is that the core would send and receive in both falling edge clocks, But I wanted to send in falling edge and receive in rising edge clock, also in the core it mentioned that it had a bug for CPHA =1

[NorthGuy]

What is easier?

(1) write 20 lines of VHDL code

or

(2) figure out how somebody else's core works?


SPI is just a sift register. You simply create a counter. Say if your clock  is 100 MHz and you want 1.75 MHz SPI, you count from 0 to 56. When it is at 0 that's your rising edge, you set CLK high and shift out MOSI. When it is at 28, that's your falling edge - you set CLK low and shift in MISO. When it's 56, you reset the counter to 0. That's all there is to it.

If the line is long, you can delay shifting MISO from 28 to a later count, or even move it to the rising edge.

[SiliconWizard]

I second that. SPI is pretty easy, write that yourself. With a couple 'generic' statements, you'll make a decently generic SPI module for all modes in a couple of hours.

The only thing to worry about for a completely generic SPI module though would be the clock domains, but that would matter only if you want to implement slave SPI, which is not what you're talking about here. Master SPI is very simple.