Are Xilinx XC7A35T actually the same die as something else or...?

[daqq]

Hi guys,

So, I've used a large buffer for something in my project, the synthesis ran and everything is OK... but I'm at 93% usage of the BRAM resources available to me. That's OK, but when I checked the synthesis device results (the actual physical representation of the device) something was weird:

There seems to be a lot of unused (and apparently unusable) BRAM left. What gives? Is it some sort of remapping? Or am I missing something weird?

Here are the device usage results. It seems that there is more physically available BRAM than there is logically. At a quick guess there seems to be around a third more BRAM that is not available.



Thanks,

David

[daqq]

Adding partial detail of left region. The BRAMs are there.

[hamster_nz]

Your thinking is correct. The validation of IDCODE in the bit stream by the  FPGA enforces the resource limit.

Thermal limits on package may also apply...

[daqq]

Thanks, minor mystery solved. Now if I could just figure out why do they do it 

[mikeselectricstuff]

ISTR reading that someone hacked this a few years ago to allow use of the undocumented RAM by tweaking the bitstream

[hamster_nz]

ISTR reading that someone hacked this a few years ago to allow use of the undocumented RAM by tweaking the bitstream

Quite a few have.

If you generate exactly the same bit stream for the two devices (and I mean exactly - routing and logic), you can XOR them with each other to discover the constant difference in the checksum that changing the id code makes. You can then apply the same changes to transmute bit streams at will.

Or you can just work out the checksum's CRC polynomial...

[rstofer]

None of which is guaranteed to work...l  It has always been common practice in the memory business to add extra rows and columns to replace cells that turn up DOA at some test operation.  Then the metal layer can map in replacement cells and map out rejects.

Looking inside may be interesting and hacking extra capabilities seems terribly clever but buying the next larger chip is a better way to go.

[Sal Ammoniac]

None of which is guaranteed to work...l  It has always been common practice in the memory business to add extra rows and columns to replace cells that turn up DOA at some test operation.  Then the metal layer can map in replacement cells and map out rejects.

Really? I strongly doubt these chips are tested before the final metal layer is added.

[asmi]

Really? I strongly doubt these chips are tested before the final metal layer is added.

It's likely the other way around - they do the tests and then laser trim out parts which don't work. At least that's how they cut off MGTs in packages that don't have them bonded out.

[SiliconWizard]

Yes I think so too. That's usually done with laser trimming.

In any case, I wouldn't do this kind of hacking on FPGAs that end up in real products... so unless it's just for the kicks on personal projects, I'm not sure how useful that would be to know this.

[filssavi]

It can be done in many ways laser trimming, fuses/anti fuses, internal flash/eprom memory read at boot

Anyways I have read somewhere (probably on Xilinx forum but don’t quote me on that) that for artix devices only 2 dies exist one for 50T and lower and the other for the higher end ones

[tmbinc]

https://github.com/brouhaha/xchange is a tool that patches the ID.

[hamster_nz]

For the FOSS IceStorm toolchain the iCE40-HX4K and iCE40-HX8K are treated identically, as they are the same die.

Works fine.

[NorthGuy]

Yes I think so too. That's usually done with laser trimming.

The die is completely the same. A50T is the same as A15T. You can use anything inside it. The overall limit on various resources is enforced by tools and the FPGA internals. Such approach has benefits for A15T - you'll never get any congestion.

[iMo]

The manufacturing of the lithography masks (you need many masks in order to produce a chip, based on technology, say 30-50) is the most expensive exercise in chip manufacturing (not counting the chip design costs itself, of course).

And a single set of masks is not enough.

It is much cheaper to produce the 50T and sell it as the 15T, than to mess with different sets of masks (ie. silicon revisions)..

PS: my guess would be a single set of masks for 50T costs something like 1.500.000,-USD

The actual production costs for a single silicon wafer full of chips is flat fee, something like 2.000,-USD per wafer (depends on the fab node, but usually 1000-2000), and you get maybe 2500 "50T" chips off a single wafer.

[mark03]

Presumably (?) one can identify which parts have identical dies by looking at the table of quiescent supply current.  Parts with the same Iq_vccint:

-12T, -25T (lowest)
-15T, -35T, -50T (middle)
-75T, -100T (high)
-200T (in a class by itself, highest)

Interestingly, for Spartan-7, the two lowest-gate-count devices (-6, -15) have lower Iq_vccint than Artix-7 12T/25T.  The higher-gate-count devices (-25, -50, -75, -100) match their Artix-7 counterparts exactly.

[hamster_nz]

Bitstream size is a good indicator.

[mrflibble]

Anyways I have read somewhere (probably on Xilinx forum but don’t quote me on that) that for artix devices only 2 dies exist one for 50T and lower and the other for the higher end ones

Too late!

The various related threads on the Xilinx forum:

• https://www.eevblog.com/forum/fpga/are-xilinx-xc7a35t-actually-the-same-die-as-something-else-or/msg2543346/#msg2543346
• https://forums.xilinx.com/t5/Other-FPGA-Architectures/Drop-in-replacement/td-p/752004
• https://forums.xilinx.com/t5/Other-FPGA-Architectures/xc7a35t-and-xc7a50t-bitstream-size/td-p/443908
• https://forums.xilinx.com/t5/Other-FPGA-Architectures/Artix-7-15t-35t-and-50t-same-chip-die-Question/td-p/705087
• https://forums.xilinx.com/t5/Other-FPGA-Architectures/Vivado-Artix-7-XC7A15T-BRAM-site-75/td-p/670657
• https://forums.xilinx.com/t5/Other-FPGA-Architectures/SPARTAN-7/td-p/883251
• https://forums.xilinx.com/t5/Other-FPGA-Architectures/migrate-from-spartan-6-to-spartan-7/td-p/815203

Short Non-super-long version:
Group by the bitstream length & quiescent current ==> die groups. I noticed that when you sort by IDCODE the die groups end up as continuous sections. Which makes sense, since that would coincide with a somewhat systematic numbering scheme on Xilinx' part. Or put another way, assuming a systematic numbering scheme of the IDCODE's grouped by die, you would end up with the sorted result as found.

Which got me these die groups:
7S15  : XA7S6, XC7S6, XA7S15, XC7S15
7A25T : XA7A12T, XC7A12T, XA7A25T, XA7S25, XC7A25T, XC7S25
7A50T : XA7A15T, XC7A15T, XA7A35T, XC7A35T, XA7A50T, XA7S50, XC7A50T, XC7S50, XQ7A50T
7S100 : XA7S75, XC7S75, XA7S100, XC7S100
7A100T: XA7A75T, XC7A75T, XA7A100T, XC7A100T, XQ7A100T
7A200T: XC7A200T, XQ7A200T

Tables for bitstream length & quiescent current taken from these docs:
* ug470_7Series_Config.pdf
* ds181_Artix_7_Data_Sheet.pdf
* ds189-spartan-7-data-sheet.pdf

[ali_asadzadeh]

It sounds a good plan for xilinx, If I where them I would do the same! just change a magic number called ID code and chnage the chip and sell if for less

Any clue about spartan 6 devices, specially the XC6SLX9-2TQG144I, I hope it could be upgraded to XC6slx25
So we can get higher density in TQFP package, Any clues out there?

[hamster_nz]

It sounds a good plan for xilinx, If I where them I would do the same! just change a magic number called ID code and chnage the chip and sell if for less

Any clue about spartan 6 devices, specially the XC6SLX9-2TQG144I, I hope it could be upgraded to XC6slx25
So we can get higher density in TQFP package, Any clues out there?

Looking at https://www.xilinx.com/support/documentation/user_guides/ug380.pdf the LX4 and LX9 are most likely the same die, but all other sizes have different bitstream lengths.

Not very helpful!

[mrflibble]

Any clue about spartan 6 devices, specially the XC6SLX9-2TQG144I, I hope it could be upgraded to XC6slx25
So we can get higher density in TQFP package, Any clues out there?

Based on the bitstream sizes listed in UG380 I suspect the answer is going to be no. You could maaaybe try downgrading to LX4 though.

[mrflibble]

About that LX4 vs LX9 ... the bitstream size is almost the same, so you might think maybe it's the same die. But chances are pretty good it's not though. While going over the 7-series dies I noticed that the 7S100 and 7A100T bitstream sizes were almost the same as well. The quiescent currents however were different. And the IDCODE's didn't fit the hypothetical nice numbering scheme either, while all the other ones did fit. So with those 3 factors combined I randomly guessed it to be more likely that the 7S100 and 7A100T are separate dies.

And coming back to the spartan-6, it would be somewhat curious for Xilinx to limit the die production cost saving measures to just the LX4 & LX9.

[hamster_nz]

It sounds a good plan for xilinx, If I where them I would do the same! just change a magic number called ID code and chnage the chip and sell if for less

Any clue about spartan 6 devices, specially the XC6SLX9-2TQG144I, I hope it could be upgraded to XC6slx25
So we can get higher density in TQFP package, Any clues out there?

Looking at https://www.xilinx.com/support/documentation/user_guides/ug380.pdf the LX4 and LX9 are most likely the same die, but all other sizes have different bitstream lengths.

Not very helpful!

Looking at table 5-5, I now think that LX4 & LX9 are most likely different...

[mrflibble]

Looking at table 5-5, I now think that LX4 & LX9 are most likely different...

Agreed. Too lazy to check the quiescent current, but expecting that to be different as well for LX4 & LX9.

[technix]

Looking at table 5-5, I now think that LX4 & LX9 are most likely different...

Agreed. Too lazy to check the quiescent current, but expecting that to be different as well for LX4 & LX9.

Is it possible that LX4 uses LX9 die but with whole sections being unpowered?