BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

[asmi]

@asmi, I'm sorry, but I cannot guarantee I will have enough free time over the next 3 months to do work on adapting my DDR3 controller to Lattice.  It's a shame that we didn't do this back in September.

No worries, that's OK, I understand, we all have a life to live.

[gvedaraj]

Hi Brian,

Just a quick question regarding the DDR3 controller. The README page says that it is designed for Cyclone 3/4/5 boards. But I see that Cyclone 3/4 supports only till DDR2.
Does that mean that the controller works for both DDR2/DDR and DDR3 memories?


Thanks & Regards
Ganesha

[BrianHG]

Hi Brian,

Just a quick question regarding the DDR3 controller. The README page says that it is designed for Cyclone 3/4/5 boards. But I see that Cyclone 3/4 supports only till DDR2.
Does that mean that the controller works for both DDR2/DDR and DDR3 memories?


Thanks & Regards
Ganesha

     No, it means wire DDR3s to a Cyclone III or Cyclone IV and it will work.

     I use a trick with Altera's PLL to generate alternate read phase clock and write phase clock which are self tuned during power-up to operate the ram.  I measure and use the DQS as a clock enable instead of as a clocking port for the DQ read data.  This permits me to control 1 or 2 16bit DDR3s on the older cyclones.  Or 4x 8bit ones.

     Use the 1.5v  HSTL CLASS I IOs and DDR3 IO voltage.  See photos and instructions of my pinouts pin-planner on my Github and review my hypothetical Cyclone III/IV examples which compile and meet timing requirements to see how to setup.

Example Cyclone III setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIII_GFX_TEST_v16_1_LAYER_Q13.0sp1

Example Cyclone IV setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIV_GFX_TEST_v16_1_LAYER

Pin planner read-me:  https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/Screenshots_Pin_Planner

[gvedaraj]

Hi Brian,

Just a quick question regarding the DDR3 controller. The README page says that it is designed for Cyclone 3/4/5 boards. But I see that Cyclone 3/4 supports only till DDR2.
Does that mean that the controller works for both DDR2/DDR and DDR3 memories?


Thanks & Regards
Ganesha

     No, it means wire DDR3s to a Cyclone III or Cyclone IV and it will work.

     I use a trick with Altera's PLL to generate alternate read phase clock and write phase clock which are self tuned during power-up to operate the ram.  I measure and use the DQS as a clock enable instead of as a clocking port for the DQ read data.  This permits me to control 1 or 2 16bit DDR3s on the older cyclones.  Or 4x 8bit ones.

     Use the 1.5v  HSTL CLASS I IOs and DDR3 IO voltage.  See photos and instructions of my pinouts pin-planner on my Github and review my hypothetical Cyclone III/IV examples which compile and meet timing requirements to see how to setup.

Example Cyclone III setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIII_GFX_TEST_v16_1_LAYER_Q13.0sp1

Example Cyclone IV setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIV_GFX_TEST_v16_1_LAYER

Pin planner read-me:  https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/Screenshots_Pin_Planner

Thanks a lot for the sharing these resources!!

[Andrp19n]

Hi, Brian
I use on my board Arria V GZ + ddr3 micron chip. When I try to compile project, I receive next error

Error (272006): The feature Dynamic Reconfiguration is not supported by the generic_pll for the Arria V GZ family.

My Quartus vaerion is 17.0.2
Do you know how to avoid this error and try out your solution?

[BrianHG]

Hi, Brian
I use on my board Arria V GZ + ddr3 micron chip. When I try to compile project, I receive next error

Error (272006): The feature Dynamic Reconfiguration is not supported by the generic_pll for the Arria V GZ family.

My Quartus vaerion is 17.0.2
Do you know how to avoid this error and try out your solution?

Give me a day to look it over.
I am not using a dynamic reconfiguration, but the my generic PLL choice may be too simple for the Arria.
For now, try setting the parameter:

parameter            FPGA_FAMILY             = "Cyclone V",

The Cyclone V's PLL is much more sophisticated compared to the older MAX10/Cyclone IV/III PLLs.  See if the PLL error still arises.  If the error is bypassed, but the ram still doesn't seem to initialize, then the final issue will be the DDR primitive IO buffer settings which I will need to update as the Cyclone V uses the old style DDR primitive call compared to the newer complete complex IO buffers used in the Max10 series.  Fixing this should take a day or 2...

[Andrp19n]

Thank you for answer! I set this parameter to "Cyclone V" and get the following error

Error (12024): WYSIWYG primitive "lcell_inst" is not compatible with the current device family

[BrianHG]

Sounds like I need to use the newer DDR IO buffers, but good news, it appears the new 'V' series PLL is good.
Please give me a day to flush out the proper 'Arria V GZ' parameters.  It's all there in my code, it is just that if you set the FPGA family to Arria V, my code just ignores it and sets the core IO & PLL primitives to the old Cyclone III/IV ones from a decade ago.

[Andrp19n]

Ok, thank you!

[Andrp19n]

Hi again! I tried to modify some parts of code and here what I got

First, I changed in BrianHG_DDR3_PLL.sv condition to FPGA_FAMILY=="Cyclone V" to be able to use altera_pll megafunction. Previous compilation error about pll disappeared, but I have new ones)

Error (10232): Verilog HDL error at BrianHG_DDR3_COMMANDER_v16.sv(1683): index 15 cannot fall outside the declared range [7:0] for vector "mask_in"

Then I changed parameter PORT_W_DATA_WIDTH[0] to 8 bit and got this pretty message. Don't even know, where to look now)

[BrianHG]

Hi again! I tried to modify some parts of code and here what I got

First, I changed in BrianHG_DDR3_PLL.sv condition to FPGA_FAMILY=="Cyclone V" to be able to use altera_pll megafunction. Previous compilation error about pll disappeared, but I have new ones)

Error (10232): Verilog HDL error at BrianHG_DDR3_COMMANDER_v16.sv(1683): index 15 cannot fall outside the declared range [7:0] for vector "mask_in"

Then I changed parameter PORT_W_DATA_WIDTH[0] to 8 bit and got this pretty message. Don't even know, where to look now)

Hello Andrp19n,

     My only 2 source files where the 'device family' makes a difference are my:

BrianHG_DDR3_PLL.sv
and
BrianHG_DDR3_IO_PORT_ALTERA.sv

The string controlling them is taken from your primary entry file:
BrianHG_DDR3_CONTROLLER_v16_top.sv
or if you are just using the my basic DDR3 controller without the 'top' then:
BrianHG_DDR3_PHY_SEQ_v16.sv


My source file 'BrianHG_DDR3_COMMANDER_v16.sv' is pure System Verilog, no Altera specific code within.
You might have a parameter error in your 'BrianHG_DDR3_CONTROLLER_v16_top.sv' with regard to the proper bit depth settings for one of your write port, or, maybe a connection port width size error.

Note, my code for each read and write port allows you to individually set the number of read and write bits down to a byte.  This means 8bits, 16bits, 32bits, 64bits, 128bits.  Using an unnatural size like 24bits or 4 bits will screw everything up.

Can I see how you instantiate my controller & how you wired the bus inputs.
This forum allows .zip file attachments to your message.
Also, I'm checking if I can get a 1 month trial Quartus 17 from intel to get Arria V support as the web version only allows Arria II.

Another note, my code was tested all the way back to Quartus 13.1 for Cyclone III support and I'm currently on Q20.1.1.

[BrianHG]

Hi again! I tried to modify some parts of code and here what I got

First, I changed in BrianHG_DDR3_PLL.sv condition to FPGA_FAMILY=="Cyclone V" to be able to use altera_pll megafunction. Previous compilation error about pll disappeared, but I have new ones)

Error (10232): Verilog HDL error at BrianHG_DDR3_COMMANDER_v16.sv(1683): index 15 cannot fall outside the declared range [7:0] for vector "mask_in"

Then I changed parameter PORT_W_DATA_WIDTH[0] to 8 bit and got this pretty message. Don't even know, where to look now)

Note about the 'mask_in' is 1/8th the write data port width.  This means an 8 bit wide write data port have a mask width of 1 bit.  A 16bit write data port has a mask size of 2 bits, ect...

[BrianHG]

@Andrp19n, another thing you can help me with is if you can make a blank dumb Arria V project.

Generate 2 verilog functions for me:

A PLL with 1 in, 4 outs, 50MHz to 400,400 at a different phase, 200 and 100.
A DDR IO port, 16 bit data  in and out, separate clocks and OE, with an 8bit DDR bus to the IO pins.

This will at lease show me which primitives the Arria V uses.  I believe the Arria V PLL should be the same as the Cyclone V pll, but the Cyclone V is a little old and I am not sure about the which DDR primitive should be used as Quartus will sometimes still allow you to compile with the wrong one, just that the IO pins will not work correctly, yet it will still simulate correctly.  (go figure...  Found out with the Max10, it uses the older Cyclone IV PLL, but a different newer IO DDR primitive ( altera_gpio_lite ) than the older Cyclone V ( altddio_bidir  (the one with the LCELL feature)) .)

Correcting these issues just means me assigning the right specifics to a new parameter value for my 'device-family'.
IE:  I will patch my github code so that everyone could use the Arria V fpga while just specifying 'Arria V' for ,y fpga_family parameter.

[Andrp19n]

Hello, Brian
There is my test project in archive. It is in VHDL, and I should create component for controlter to be able to instantiate it. There are also two folders inside - io_port and test_pll with two verilog functions. I used ALTDDIO_BIDIR component to create io_port. And BrianHG_DDR3_PLL.sv was modified at 305 (FPGA_FAMILY=="Cyclone V")

[BrianHG]

@Andrp19n.  Ok, you are doing 2 things at once.

Looking at pgk_lib.vhd, line 22, you have

     FPGA_FAMILY :string := "Arria V GZ";

Instead of := "Cyclone V"...
You weren't supposed to edit the 'xxxx_PLL.sv' source file.

----------
OK:
You have given me enough to properly patch my PLL and IO port source files.
  I'll upload them in the morning...
---------

Now VHDL is not in my book, but the best first thing to do is to see if my DDR3 is functional.
Do you have an RS232 port on your board, or, 2 spare IO pins and a LVTTL <-> RS232 USB serial cable for your PC?

If so, take this project from my github / or / you should already have this folder.:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_DECA_RS232_DEBUG_TEST_v16

Copy and rename the project.  Then change the FPGA to your Arria V GZ fpga.  Delete the unused IOs, remap the DDR3 IOs and the RS232_RX/TX pins.

Change one line 21 of BrianHG_DDR3_DECA_top.ss the FPGA family to 'Cyclone V' (temporarily until I fix my source to include 'Arria V') and see if you can get it to compile.

If you can get it to compile, download my RS232 debugger.exe and see if you get the status bits going and if you can read/write a few bytes to your onboard DDR3.

[Andrp19n]

I didn't want to change source files except for test purposes. If I define "Cyclone V" family, I get this error:

Error (12024): WYSIWYG primitive "lcell_inst" is not compatible with the current device family

Editing helped me to bypass PLL compilation error. Anyway, I discarded all changes in source files, thanks for help!

About debugging. The only way to check ddr3 functionality for now on my board is trying to read/write some data

[BrianHG]

@Andrp19n.  Ok, try my updated PLL source file.

Just set your FPGA_FAMILY on pgk_lib.vhd, line 22 to:

     FPGA_FAMILY :string := "Arria V GZ";

If you now use an unknows FPGA_FAMILY string, my PLL will also stop the compiler and spit out an error message in the compiler message window.


Also, if you get another Quartus compiler error, please include a few additional lines prior to the error message in the error log.

Code: [Select]

// Version 1.3, April 5, 2024
//   *** New, added Arria V GX, GT, SX, ST, GZ pll support to line 288 & selecting which PLL at line 335.
//       Also added a $stop & $error message if the FPGA_FAMILY is Unknown at line 310.


According to the datasheet, the fastest Arria Vs should officially achieve an 800MHz DDR3 controller, meaning an official 1.6gtps data rate.

However, since I cannot compile for the Arria V, I cannot tune the .sdc file.  However, with the existing entries where I list the optimum -8,-7-,6 optimum cyclone devices, the Arria V -5,-4,-3 may be inferred.

I've downloaded the full paid Quartus to see if I can get the 1 month free full support.  If it works, I'll know if everything will simulate and tune the best .sdc as my DDR3 controller uses an FPGA centered IO timing system.  Meaning: all the IO ports were just need to have a best possible minimal pin-to-pin skew.  At power-up, my controller then measures the return-read data timing read from the DDR3 automatically adjusting to the IO pin delays and PCB trace lengths.

[Andrp19n]

Hi! Thank you! Pll error compilation has now disappeared. But I still get this error

Error (10232): Verilog HDL error at BrianHG_DDR3_COMMANDER_v16.sv(1683): index 15 cannot fall outside the declared range [7:0] for vector "mask_in"

I have MT41K512M8 memory, which has 8bit DQ. So I set these parameters:
DDR3_WIDTH_DQ = 8
DDR3_WIDTH_DM = 1
DDR3_WIDTH_DQS = 1

When these parameters are set as for 16bit DQ, this error doesn't appear. Only these 3 parameters and "FPGA_FAMILY" are different from defaults. Did I miss something?

[BrianHG]

Hi! Thank you! Pll error compilation has now disappeared. But I still get this error

Error (10232): Verilog HDL error at BrianHG_DDR3_COMMANDER_v16.sv(1683): index 15 cannot fall outside the declared range [7:0] for vector "mask_in"

I have MT41K512M8 memory, which has 8bit DQ. So I set these parameters:
DDR3_WIDTH_DQ = 8
DDR3_WIDTH_DM = 1
DDR3_WIDTH_DQS = 1

When these parameters are set as for 16bit DQ, this error doesn't appear. Only these 3 parameters and "FPGA_FAMILY" are different from defaults. Did I miss something?

I just compiled a 8-bit DDR3 version of my Cyclone IV project and it went fine.

The 'BrianHG_DDR3_COMMANDER_v16.sv' module has a width limit on the multiport read & write data widths:

Code: [Select]

parameter bit [8:0]  PORT_R_DATA_WIDTH [0:15] = '{  8, 64, 32, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
parameter bit [8:0]  PORT_W_DATA_WIDTH [0:15] = '{  8, 64, 32, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
                                                // Use 8,16,32,64,128, or 256 bits, maximum = 'PORT_CACHE_BITS'
                                                // As a precaution, this will prune/ignore unused data bits and write masks bits, however,
                                                // all the data ports will still be 'PORT_CACHE_BITS' bits and the write masks will be 'PORT_CACHE_WMASK' bits.
                                                // (a 'PORT_CACHE_BITS' bit wide data bus has 32 individual mask-able bytes (8 bit words))
                                                // For ports sizes below 'PORT_CACHE_BITS', the data is stored and received in Big Endian. 

Basically, with a single 8bit DDR3 ram chip, you cannot go above 64bits for each read and write channel.
IE: Only 8,16,32,64 bits on each channel are valid.


As for your ram chip settings, for a 4gb DDR3 ram chip with 8 bits, you should have: (MT41K512M8 – 64 Meg x 8 x 8 banks)

Code: [Select]

parameter int        DDR3_SIZE_GB            = 4,                // Use 0,1,2,4 or 8.  (0=512mb) Caution: Must be correct as ram chip size affects the tRFC REFRESH period.
parameter int        DDR3_WIDTH_DQ           = 8,                // Use 8 or 16.  The width of each DDR3 ram chip.

parameter int        DDR3_NUM_CHIPS          = 1,                // 1, 2, or 4 for the number of DDR3 RAM chips.
parameter int        DDR3_NUM_CK             = 1,                // Select the number of DDR3_CK & DDR3_CK# output pairs.
                                                                 // Optionally use 2 for 4 ram chips, if not 1 for each ram chip for best timing..
                                                                 // These are placed on a DDR DQ or DDR CK# IO output pins.

parameter int        DDR3_WIDTH_ADDR         = 16,               // Use for the number of bits to address each row.
parameter int        DDR3_WIDTH_BANK         = 3,                // Use for the number of bits to address each bank.
parameter int        DDR3_WIDTH_CAS          = 10,               // Use for the number of bits to address each column.

Again, my 'commander' module is only a multi-channel front-end, it has no DDR3 or Altera specific code.
I've attached my 8bit DDR3 CycloneIV project.  It contains my full multiwindow graphics subsystem with a drawing and scrolling algorythm with RS232 debugger.  It appears to compile fine.

[BrianHG]

@Andrp19n, in the VHDL file you send me, pkg_lib.vhd:

Lines 63,64:

Code: [Select]

PORT_R_DATA_WIDTH: array_of_std_logic_vector(0 to 15)(8 downto 0) := ("010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000");
PORT_W_DATA_WIDTH: array_of_std_logic_vector(0 to 15)(8 downto 0) := ("010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000");

You have the read and write ports bit width set to 128.  Like I said, with a single 8bit DDR3, the maximum you can use is 64, otherwise you will get a compiler error.

The max port width for 16bit DDR3 would be 128 and the max port width for a 32bit DDR3 controller would be 256.

Maybe changing the "binary" representation into an integer would help catch these bugs.  On a hunch, I double checked by counting the binary '0's in your code.

[BrianHG]

New PLL v1.4.
PLL now supports up to 1GHz for Arria V and Cyclone V, this means up to 2gtps.

Note that the original PLL was capped at 600MHz/1.2gtps which was the Cyclone V over-clock-able limit.

[Andrp19n]

Hello
Finally, I have compiled library in vhdl project. There were some issues with translating from sv to vhdl. However, I still couldn't launch the memory. Keep working on that. Thanks for help