Project idea: GSP referenced clock.

[hamster_nz]

If anybody is looking for an intermediate project, or maybe one for their GitHub portfolio...

The MMCM block on the Artix 7 has a fine phase shift adjust. It shifts 1/32nd of the VCO frequency.

With a VCO frequency 0f 600MHz, that is about 50ps per shift, with a 1200MHz that is 25ps. You can shift about once every dozen of the phase shift control clock, allowing you to pull/push the VCO about 390kHz, and when divided down to 100MHz that is about between 30kHz and 60kHz. That pull range is more than enough to cover the PPM accuracy range of a development board's on-board oscillator (usually around +/-50ppm)

So with just a GPS module and a well designed control loop, it should be quite possible to generate a 'pretty good' PPS-referenced signal (not as good as a true VC-TCXO, but still good enough to be interesting to evaluate).

I feel it is an interesting project as:
- It covers a small corner control loop theory
- Is a simple FPGA design (< 500 LUTs, maybe a 1000 lines or so of HDL)
- Makes use of an advanced FPGA feature that relatively simple to use MMCM's phase shift).
- Involves multiple clock domains and most likely a simple clock domain crossing
- Is low cost (just dev board + ~$10 GPS module)
- It is quite interesting to predict and then validate the performance of such a design
- You can use the other features of the dev board (switches, LEDs, 7-segs) to display status and trim

What do others think? Does it tickle anybody's interest?

[Foxxz]

Are you asking people into a group project or just throwing out ideas to pad people's resume?

[hamster_nz]

Are you asking people into a group project or just throwing out ideas to pad people's resume?

Just the idea throwing it out there... maybe for a student in need of a project?

I don't think it is 'padding' on a resume. People are at their best talking about things they have invested their time and effort into and found interesting. When interviewing people people for FPGA roles we are often pointed at GitHub or other repos for examples of their work.

If I get the chance to review their code I take it. It is quite good way to assess their skill level and allows the interview to talk with them about their design decisions on a code base that they are familiar with, and makes the interview more interactive. Do they correctly implement synchronizers, if not, why not? How do they deal with resets? What structures do they prefer to infer, and what do they instantiate? Do they show an awareness of the underlying FPGA architecture? How do they test it?

A lot of people have things like a CPU core or FIR/IIR/CIC DSP filters and other fully synchronous designs with a single clock domain. If you are lucky there might be a PLL in there somewhere, generated using the clocking wizard or IP builder.

This project would be something novel to see, and at the same time is a small but interesting project in its own right for somebody to spend a few nights designing.

[MIS42N]

Just curious. Does the exercise have a purpose, or is just something to test skills?

[ejeffrey]

Just curious. Does the exercise have a purpose, or is just something to test skills?

I'm not sure if hamster_nz has a specific use in mind but there are definitely times when you want not only to have an accurate GPS disciplined clock but to have the FPGA core clock synchronous with it, for instance low jitter data sampling.  Normally you do that with an external GPS-DO and then clock the FPGA with that, but this requires a bunch of extra components, and it won't be available on a cheap dev board.  So I think it is kind of interesting that you can do it with a standard fixed frequency XO and the built-in phase shifter.  I'm not sure I would actually use it for many of the situations where I want precision time stamping or whatever, but it would definitely be a neat demo and could be useful in situations where you didn't have a choice but to use a cheap dev board.

It might also be possible to improve the performance of an existing instrument with essentially no extra hardware.  For instance, a lot of small volume test equipment already have similar cheap FPGAs in them.  This could allow one to be upgraded to support GPS time sync for the cost of a single GPIO.

[hamster_nz]

I got bored last night and implemented this design. The design is pretty much all in one file:

https://github.com/hamsternz/MMCM_GPSDO/blob/main/gps_xo.vhd

To quote the README.md:

Using a BASYS3 development board, if a GPS module's PPS input is connected to JB0 clk signal will be soon be locked to the GPS system's time reference. LEDs 14:0 show the current error in HZ, and LED15 show if it is locked.

Well, by locked I mean it will have a frequency that is kept within one part per million of GPS time.

The control loop is woefully engineered, and the size of all the registers has been (not) optimized for coding simplicity, and all the constants are empirically derived, but it works as advertised.

Plenty of room for experiment and improvement.

[colorado.rob]

This is great. I have been playing around with RF DSP stuff and having an accurate internal reference using a cheap GPS 1PPS input is going to be a nice addition.

I have not looked at the implementation yet. What does this do to clock jitter?