Indexed pins in constraints file?

[Shimonu]

Just started using an FPGA recently and got the master file for my development board. Something I noticed was how the pins were declared there using brackets, like this

Code: [Select]

set_property -dict { PACKAGE_PIN "K12"   IOSTANDARD LVCMOS33}   SLEW FAST} [get_ports { LED[0] }];                     
set_property -dict { PACKAGE_PIN "K13"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[1] }];                     
set_property -dict { PACKAGE_PIN "R10"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[2] }];                     
set_property -dict { PACKAGE_PIN "R13"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[3] }];                     
set_property -dict { PACKAGE_PIN "T13"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[4] }];                     
set_property -dict { PACKAGE_PIN "R12"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[5] }];                     
set_property -dict { PACKAGE_PIN "T12"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[6] }];                     
set_property -dict { PACKAGE_PIN "R11"   IOSTANDARD LVCMOS33    SLEW FAST} [get_ports { LED[7] }]; 

But how am I supposed to use them? I can't just declare LED[0] as an output, I get an error that I can't declare LED as an array. I'm assuming this is to easily use the LEDs as a group but can I still just bring one LED into a top file? So are my options to rename them or use LED as a bus?

[langwadt]

you declare LED as an 8bit output port

[glenenglish]

yep
like this. now the tool will be able to connect the dots.
(VHDL)
GENERIC (
   NLEDS      :    integer :=8
   );
    Port (
      LEDS : out STD_LOGIC_VECTOR(NLEDS-1 downto 0)

   

[hamster_nz]

yep
like this. now the tool will be able to connect the dots.
(VHDL)
GENERIC (
   NLEDS      :    integer :=8
   );
    Port (
      LEDS : out STD_LOGIC_VECTOR(NLEDS-1 downto 0)

Note that the signal name must match in upper/lower case, as well as in singular vs plural  (note how the constrains used "LED", but this code snippet uses "LEDS".

[ejeffrey]

I'm assuming this is to easily use the LEDs as a group but can I still just bring one LED into a top file? So are my options to rename them or use LED as a bus?

I don't quite get what you are wanting to do.  You declare LED as a bus in the top level module but you can access them individually which the module body.

[pcprogrammer]

In verilog you also list them as a bus like below.

Code: [Select]

module MyModule
(
  output wire [7:0] LED
);

Within the code you can use either the whole bus or parts of it or just a single one.

Code: [Select]

assign LED[0] = 0;

assign LED[7:4] = 1;

More on this can be found here or here.

[glenenglish]

verilog : "assign LED[7:4] = 1" 

VHDL would never allow such a thing ! More reasons VHDL is the real mans HDL.

[langwadt]

verilog : "assign LED[7:4] = 1" 

VHDL would never allow such a thing ! More reasons VHDL is the real mans HDL.

you like fishing?

[SiliconWizard]

yep
like this. now the tool will be able to connect the dots.
(VHDL)
GENERIC (
   NLEDS      :    integer :=8
   );
    Port (
      LEDS : out STD_LOGIC_VECTOR(NLEDS-1 downto 0)

Note that the signal name must match in upper/lower case, as well as in singular vs plural  (note how the constrains used "LED", but this code snippet uses "LEDS".

The plural thing was fun.

Regarding case, VHDL is actually case-insensitive so it doesn't matter. Still, for style and consistency reasons, I strongly suggest always writing a given identifier in exactly the same way case-wise. But it's not required.

[AK6DN]

In verilog you also list them as a bus like below.

Code: [Select]

module MyModule
(
  output wire [7:0] LED
);

Within the code you can use either the whole bus or parts of it or just a single one.

Code: [Select]

assign LED[0] = 0;

assign LED[7:4] = 1;

More on this can be found here or here.

Better to write:

Code: [Select]

assign LED[7:4] = {4{1'b1}};

or

assign LED[7:4] = 4'b1111;

as what you have written is really:

assign LED[7:4] = 4'b0001;