Noob: How to program XC9500XL-series dedicated global IO signals

[obiwanjacobi]

Hi, Beginner here.

I am working on a project that has a XC95288XL (144 pin) on it and I am trying to understand how to program the dedicated global IO pins.
Specifically the Global Set/Reset (GSR) and the Global Three State (GTS) pins.

I use the ISE WebPack 14.7 software (Project Navigator) for compiling the VHDL code.
Datasheet: https://www.fpgasemi.com/datasheet/fpgasemi/XC95288XL-10TQG144C.pdf

I see on page 6 of the datasheet that the GSR first goes through a mux to select active low or hi operation (I assume).
I want to program that to active low. Then I would like to reset all 288 FFs when the GSR is activated.

For the (four) GTS pins, I just want to select some of my outputs to go hi-Z.
But I have no idea how to get the tooling to do that (both GSR and GTS) (and how to test it - for that matter).

Can anybody point me in the right direction?

Additional question: Is it possible to repurpose these pins (GSR,GTSn,GCKn) for general IO?

[bson]

In SystemVerilog:

Code: [Select]

module top(
     inout wire io_pin
  );

  logic pin_dir;
  var logic some_input;
  logic some_output, clk;

  always @(posedge clk) begin
    if (pin_dir)
      io_pin <= some_output;
   else
      some_input <= io_pin;
  end
 
  // ...

endmodule

Tri-state just means the pad is set to input and you ignore some_input elsewhere.

The synthesizer will automatically change the direction as needed.  Effectively, inout ports have three interconnects: one for input, one for output, and for the direction to switch between the two.  The I/O pad will have the same three connections.  Only use inout ports for external I/O pads; while you can use them between internal modules it's better to have separate in/out buses or signals with common rd/wr or enable/dir signals.

[obiwanjacobi]

So basically you program/duplicate the logic that the CPLD provides in the HDL and choose the correct dedicated pins and the compiler/fitter will be able to match it up?

How do I tell it to set the GSR mux that determines the active-low/high operation of the reset line?
And what happens if one module uses a /rst (active low) and another uses rst (active high)?

[xvr]

So basically you program/duplicate the logic that the CPLD provides in the HDL and choose the correct dedicated pins and the compiler/fitter will be able to match it up?

Yes

How do I tell it to set the GSR mux that determines the active-low/high operation of the reset line?

Write appropriate HDL code

And what happens if one module uses a /rst (active low) and another uses rst (active high)?

The fitter will use the GSR as a normal input and set/reset the triggers at the appropriate levels via the interconnect matrix.
The fitter can use either a dedicated GSR network or an interconnect (if it's intelligent enough), implementing one level in the GSR and the other through the GP network.