Lattice Diamond verbose synthesis engine errors

[lk.dgironi]

Hello,

I'm working on a ECP5 project.
I'm using Lattice Diamond 64bit 3.12.1.454 on Windows 10 x64.
I usually write it in Verilog, using LSE as synthesizer.
It happens that I mistype something. Even something simple like a wire without the ending.
When it happens the only error i get on Output tab is something like:
-- Verilog file '___filefullpath___.v' ignored due to errors (VERI-1483)
ERROR - Failed to analyze design file '___filefullpath___.v'.
Done: error code 2
Error, Warning, Info tab does not help.
I'm wondering if there's some setting I can use to enable a higher verbose to catch the error.

Thanks!

[ale500]

While I normally avoid LSE and use synplify instead (produces smaller designs), its default error reporting can be sketchy too. In such cases, I run synplify manually from the tools menu, it provides more verbosity and describes those "error 9" enough that I find what I misspelled or borked.

[lk.dgironi]

Thanks!
One question about Synopsys. As far as i know Symplify is not free. Am i right?

~ Previously reply with my other account, my mistake ~

[ale500]

Diamond has both of them, and synplify (yeah, with 'n') is free with it.

[lk.dgironi]

Thank you, I thought it was an on fee component.
I'll try it!

... (yeah, with 'n') ... one of the typo error I was speaking about LOL

[SiliconWizard]

Yes, both are free to use in Diamond. LSE has some benefits in some specific cases, it's also usually faster. Pick what works best for you.

Lattice is one of the few (if the only one?) vendors to provide both Synplify and their own synthesis engine, for free.
Most others either provide one or the other.