Hi all,
I just open-sourced a hardware security SoC I designed
independently, targeting Fabless tapeout on SKY130.
Three-layer security architecture:
- 64-stage RO-PUF: chip-unique 64-bit fingerprint
(Hamming weight = 32/64, verified)
- 6-state anomaly detection FSM: zero-cycle alert latency,
permanent hardware lock
- ARX hash engine: 128-bit identity token + Phys-XOR audit chain
Verified with Icarus Verilog 12.0 on EDA Playground:
61 test cases, 100% pass rate on all three core modules.
Targeting ChipFoundry shuttle CI2609 (SKY130).
The entire design was done on a mobile phone —
no computer, no commercial tools.
GitHub:
https://github.com/maomaoati-coder/SiliconForge-Security-SoCHappy to discuss the design or verification approach.