program working in xilinx not in altera

[electros6]

Hi guys,
          I wrote code to drive 7 segment display using MAX7219. The code works fine in xilnx spartan6 and the display show as intended ,but if I used the same code after proper pin set in altera cyclone II EP2C5T144  the display not showing anything. After programmed  I checked the waveforms in both xilinx and altera it shows same waveform. please anybody know the reason.

[ataradov]

Show us the code maybe?

[Neilm]

I would guess a synthisis or placement issue. You may have got lucky with how the Xilinx programme routed internal signals, but ended with the Altera chip having a race condition due to improperly specified constraints

[daqq]

Did the compiling for the Altera device give any warnings? Are the IO voltages the same? Are the clock speeds the same? Is it a known good device you are testing it out on?

You are giving too little information.

[Sferix]

You really haven't given enough information.  When you say both cases produce the same waveform what do you mean, in simulation on a scope or something else ?  When you say   
"after proper pin set" do you mean you have correctly set your I/O configuration in both cases ?  You might also include the code as already suggested.

If the code really is producing the same waveform I would suspect I/O configuration could be the problem.  Are you sure you have correctly set your I/O configuration in both cases.  E.G. I/O driver type, voltage levels, drive strength, pull ups, etc.  Sadly the tools can be quite confusing on this.  Good luck.

[rstofer]

Common anode versus common cathode?  The SAME display or a second display that may be a different design?
Dropping resistors on-board or off-board?  Factory board with display or external display?

[electros6]

I used the same display for both the fpga. I checked the waveforms using the scope.

here is the code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity display is
 port (
        clk : in std_logic;
        sclk : out std_logic;
      din : out std_logic;
      cs : out std_logic );
end display;
   
architecture Behavioral of display is

  signal sclk_clk_div : std_logic_vector (10 downto 0):="00000000000"; -- counter for serial clock
  signal dig_count : std_logic_vector (3 downto 0):="0000"; --counter for display select
  signal sclk_s : std_logic:='0';
  signal cs_s : std_logic:='0' ;
  signal din_s : std_logic:='0' ;
  signal st :std_logic:='0';
  signal dig_data : std_logic_vector (7 downto 0):="00000000"; --data to the display
  signal dig_add : std_logic_vector (7 downto 0):="00000000"; -- address to the display
  signal dig_data_add : std_logic_vector (15 downto 0):="0000000000000000";
  signal c :std_logic_vector(4 downto 0):="00000";
 
  begin                  
    process(clk)   
     begin
     if clk'event and clk = '1' then
       if sclk_clk_div = "11000000000" then
        sclk_clk_div <= (others => '0');
       else
          sclk_clk_div <= sclk_clk_div+1;
       end if;
      end if;
      
       sclk_s<= not sclk_clk_div(5);
      -- cs_s <= sclk_clk_div(10);   
    end process;
   
     dig : process(cs_s)
    --  variable dig_count: integer := 0;
      type digit is array ( 0 to 7 ) of std_logic_vector(7 downto 0);
      constant dig_data_array : digit := ("00001000","00000111","00000110","00000101","00000100","00000011","00000010","00000001");
     begin
      if cs_s'event and cs_s = '1' then
          dig_count <= dig_count + 1;
          case dig_count is
            when "0000" => dig_data <= x"01" ; dig_add <= x"0C" ;  --set to normal mode
            when "0001" => dig_data <= x"FF" ; dig_add <= x"09" ;  -- set to codeB decode
             when "0010" => dig_data <= x"07" ; dig_add <= x"0B" ;  -- set to scan all
            when "0011"=> dig_data <= x"0A" ; dig_add <= x"0A" ; -- set to 21/32 intensity
            when "0100" => dig_data <= dig_data_array(0) ; dig_add <= x"01" ;
            when "0101" => dig_data <= dig_data_array(1) ; dig_add <= x"02" ;         
              when "0110" => dig_data <= dig_data_array(2) ; dig_add <= x"03" ;
            when "0111" => dig_data <= dig_data_array(3) ; dig_add <= x"04" ;
            when "1000" => dig_data <= dig_data_array(4) ; dig_add <= x"05" ;
            when "1001" => dig_data <= dig_data_array(5) ; dig_add <= x"06" ;
            when "1010" => dig_data <= dig_data_array(6) ; dig_add <= x"07" ;
            when "1011" => dig_data <= dig_data_array(7) ; dig_add <= x"08" ;
            when others => dig_data <= x"00" ; dig_add <= x"FF" ;
          end case ;
         
      end if; 
      if dig_count = "1100" then
        dig_count <= "0100";
      end if;
       
    end process ;
   
    -- start : process (cs_s)
    --  begin
   --     if cs_s'event and cs_s = '0' then
   --      st <= '1';
   --     elsif cs_s'event and cs_s = '1' then
   --      st <= '0';
    --    end if;        
   --   end process ;   
 
      ser : process (sclk_s)
      
      begin
         if sclk_s'event and sclk_s = '0' then 
        --  if st = '1' then 
           if c <= 15 then
            din_s <= dig_data_add(15);
            dig_data_add(15 downto 1) <= dig_data_add(14 downto 0);
            dig_data_add(0) <= '0';
            c <= c + 1 ;
           end if;
           if c = "10000" then
             cs_s<='1';
             c <= c+ 1;
             dig_data_add <= dig_add & dig_data;         
          end if;
           if c= "10001" then
            c <= (others => '0');
            cs_s<='0';
            end if;
        end if;
        end process;   
      
      sclk <= ((sclk_s));
      din <= din_s;
      cs <= cs_s;
      
    end Behavioral;
      

[Ice-Tea]

Not sure if this is your issue but you have a digcount issue... In one part you add one, in another you compare and assign another value. Only one can happen during a clock cycle. Not sure which one the compiler would pick. Either there's a rule for it (don't know) or this is up to the compiler in which case this might je the reason for the difference.