Cyclone 10 LP IO restrictions

[jbb]

Hi all

Just thought I’d post a message about a pit I almost fell in at work…

First up: the Cyclone 10 LP and GX are very different inside. I think it’s kinda malpractice for Altera to do call them both ‘Cyclone 10.’

The Cyclone 10 LP devices are fussy about IO:
[ol]

• Build a placeholder project in Quartus with all your IO and run a synthesis before you order boards. There are numerous IO rules which aren’t listed in the handbook and only come out during synthesis. You would think that the Pin Assignment tool would be able to check things (or, I don’t know, help you…) but I haven’t seen a button for it.
• LVDS outputs only available on IO Banks with 2.5 V supply.
• Proper LVDS outputs only available on side IO Banks 1, 2, 5?, 6?. Other banks require 3 resistors to emulate LVDS transmission
• The IO banks with proper LVDS outputs have fewer LVDS pins available.
• If using SPI flash (aka Active Serial programming), that seems to require a 3.0 or
  3.3 V supply on IO Bank 1. Which is annoying because that takes out a quarter of the LVDS transmitters!
• There are rules about how close a single ended output OR input can be to a differential IO. It’s about the location of silicon IO pads on the die, so you need to go into Pin Assignments tool and find to the Pad View to see them. Trying to share single ended IO with differential IO is thus rather annoying
• Be wary if your design calls for lots of LVDS IO, because it can get tricky…

[/ol]

[BrianHG]

Use the TrueLVDS if you are getting close to the bandwidth limits of pairs.

The emulated LVDS IOs still work fine at lower frequencies (available on all banks).  Its less about the voltage ranges and more about the bandwidth and tightness and jitter.  If you want the >500mbps, you should probably stick with the TrueLVDS, though, I have overclocked the Cyclone series emulated LVDS to 1gbps, bidirectional error free.

Also, if the FPGA is the master clock generator and output driver, you can easily get away with maxing out the specs.  If the FPGA is the clock generator and you are receiving LVDS, timing constraints become crucial.

You can still run the emulated LVDS at 3.3v IO levels, but again, this is not officially supported at 640msps.