Looking for resources, FIR filter design / coding

[AussieBruce]

I want to implement a FIR LP filter in verilog. Is anyone aware of a free or economical resource for designing these and generating verilog code? I'd love to have the Matlab toolkit but the other half isn't too keen on the cost (this is a hobby venture).

[BrianHG]

Try www.opencores.org.

[ali_asadzadeh]

https://zipcpu.com/dsp/2017/09/15/fastfir.html

[asmi]

I don't know what FPGA are you planning to use, but I know for sure that both Xilinx and Altera IDE have free IP cores for these filters. Take a look at them and see if you can employ them.