Sorry, I don't recall my Verilog well enough to debate this. The issue is not the statements within a process (module). It's the ordering of the execution of the clocked logic in different modules.
Consider module A assigns output X on the clock edge CLK. Module B assigns output Y on clock edge CLK. If X depends on Y and Y depends on X, you get different results depending on which process is executed first.
That is not true, in either language (assuming non-blocking assignments in Verilog).
Remember how assignments work:
On the event that triggers the process -- the rising edge of the clock -- all right-hand-sides of assignments are captured. Remember a "right-hand-side" also includes the conditions in
if statements, the expressions in
case statements, and the like. Then each line in all of the processes sensitive to the clock are evaluated. In a given process the lines are evaluated in order. After each evaluation, the result of that evaluation is scheduled to be assigned to the target on the left-hand-side. Only after all assignments are evaluated and scheduled do the left-hand-sides actually update.
Let's look at a simple example:
Swap1 : process (clk, rst_l) is
begin
if rst_l = '0' then
X <= '1';
Y <= '0';
elsif rising_edge(clk) then
X <= Y;
Y <= X;
end if;
end process Swap1;Now the same process but with the assignments after the clock edge test reversed:
Swap2 : process (clk, rst_l) is
begin
if rst_l = '0' then
X <= '1';
Y <= '0';
elsif rising_edge(clk) then
Y <= X;
X <= Y;
end if;
end process Swap2;If the assertion, "you get different results depending on which process is executed first" was true, then you'd get different results with these two processes.
But you don't. They are identical. Which is as you would expect.
And that is because at the clock edge, the current values on X and Y are both captured. Then (since the evaluation is trivial) we simply assign the current value of X to Y, and the current value of Y to X. On the next clock edge, you have new current values on X and Y. And so forth.
Simulate the two examples. Prove to yourself that what I say here is correct. And yes, I realize that the example is trivial.
If you are using VHDL variables, then yes, the order in which the statements in the process are written absolutely matters, because a variable updates immediately after evaluation, instead of having the evaluation result scheduled for assignment. For example:
Swap3 : process (clk, rst_l) is
variable v_foo : std_logic;
begin
if rst_l = '0' then
v_foo := '0';
X <= '0';
Y <= '0';
elsif rising_edge(clk) then
X <= v_foo;
v_foo := BAR or BLETCH;
Y <= v_foo;
end if;
end process Swap3;versus:
Swap4 : process (clk, rst_l) is
variable v_foo : std_logic;
begin
if rst_l = '0' then
v_foo := '0';
X <= '0';
Y <= '0';
elsif rising_edge(clk) then
v_foo := BAR or BLETCH;
X <= v_foo;
Y <= v_foo;
end if;
end process Swap4;In Swap3, the current value of v_foo is assigned to X, then v_foo gets a new value, and that new value is assigned to Y. On the next clock, the value we assigned to Y -- the current value of v_foo -- on the previous clock is assigned to X, and then again v_foo gets a new value which we assign to Y.
In Swap4, v_foo is assigned a new value on the clock edge, and that value is assigned to both X and Y.
So for variables the order of evaluation in the process matters.
As for Verilog: the assignment semantics are identical to what I describe above if you use non-blocking assignments in your always block. If you use blocking assignments, then the evaluation and updating are the same as for VHDL variables, which means the order in which assignments are evaluated matters and you will get different results depending on how you write the block.
Hope this helps.
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