Phase sync two same frequency input's ?

[sunilsha]

I am trying to implement a phase correction verilog module for two clock inputs coming into my cycloneiv fpga.

My module has
Two clock signals, clock_1 and clock_2 with frequency 8Khz from different clock sources that are input to the fpga pins, and a ref_clk 25Mhz to sample the signals. I have an output of the module phase_sycned_out.

Requirement:
I need to come up with a verilog logic which preserve's the phase information of clock_1 and then uses the standalone clock_2 to delay clock_2 by the necessary cycles so as to match the clock_1's phase. This delayed clock_2 is to can be further output on phase_synced_out of the fpga. This is the 1st step of my problem.

Regards
-sunilsha

[Rainwater]

Would measuring phase difference between two digital inputs of he same frequency would be as simple as measuring the time between rising edges or am I missing something?

[hamster_nz]

The easiest way I could see is a 4096 x 1 bit memory - that allows for up to 163us of delay.

A free-running write counter in the 25MHz domain is used to write the reference signal to the memory.

An offset behind the write counter is used to read the memory, and send to the output.

You have a phase comparator comparing the input and output, and use that to adjust the offset

Code: [Select]

   on a clock_25MHz
        ram[wr_addr] <= ref_input;
        ref_output <= ref_input;
        tracking_output <= ram[wr_addr - delay/64];
        # Rising edge of ref clock
        if ref_output = '0' and ref_input = '1' then
            if tracking_output = 1 then
               #we are leading, so increase the delay
               delay++;
            if tracking_output = '0' then
               #we are lagging, so decrease the delay
               delay--;
      wr_addr++;

Note that such a thing will only work if both of the slow clocks come from the same reference - if not, eventually you will need to skip / insert an extra cycle to keep synced.

You could code it a lot more subtilly than this, but as a 0th approximation it should be workable.