Electronics > FPGA

SD card/SDIO 3.0 level translation solution

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I'm working on adding SD/SDIO card slot to my FPGA board, but there is a problem - UHS-I cards require switching from 3.3V to 1.8 V logic level during the course of work in order to get maximum performance out of cards. As changing IO standard on a fly is not possible, the only solution is some sort of level translator. Unfortunately the only solution I've found in stock (IP4856CX25) is 0.4 mm pitch BGA which require microvias and raises the price of a board to a stratosphere. So I wonder if anybody over here has any solution for this problem.



--- Quote from: sd on November 13, 2018, 05:00:48 pm ---http://www.ti.com/lit/ds/symlink/txs02612.pdf

--- End quote ---
This one is only rated to 60 MHz, while SDR104 requires 208 MHz clock, so it's not SD3.0 compliant and can't get full UHS-I throughput. Some other TI parts like SN74AVCA406 are also no good as they are rated up to 95 MHz.
The only solution I can think of right now would be to use 1.8V logic standard on FPGA, but then use hi-bandwidth analog switch (like TS3A27518) to switch in 1.8->3.3 V voltage translator during boot-up when 3.3V signalling is required, but switch it off to straight-through connection to FPGA once the bus is switched to 1.8 V. Since SD boot sequence until bus voltage switch is short and no high frequency is required, I can get away with pretty much any translator as long as channel-to-channel skew won't be too large,

As I hope to design an I.MX RT10xx board in the near future, and these MCUs claim to support UHS-I, I was curious how NXP handled this on their eval board.  Turns out they have a separate VCC for the IO bank containing the SD signals, and this rail comes from an adjustable regulator which they switch between 1.8 and 3.3 volts on the fly.

I am a rank beginner with FPGAs.  What happens if you define the IO standard as LVCMOS 3.3 and then step VCCO for that IO bank down to 1.8V?  What does switching the IO standard between LVCMOS 1.8/2.5/3.3 actually *do*, physically?

I have no idea how to do it smart ... but I have an idea how to do it expensively.

Connect the SD-connector to something like a MAX4996 and then to slow level converter to do communication at HS, then when it switches SDR104 switch to a separate set of pins on your FPGA with the MAX4996. Needs extra pins on the FPGA, but only one IO voltage.


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