Hello,
I have 2 reference clocks, both are precise (+/-1µs) and give pps output. They suffer from different problems:
- The first one is intermittent (GNSS PPS signal)
- The second one is intermittent and also sometime strongly wrong: every few minutes, 5-6 consecutive pulses are far away from the "reference" clock. They are so wrong that they are easily detectable (error in tenth of µs to tenth of ms).
Adding a good TCXO in the loop, it must be possible to build something that always give a PPS, switching between the 2 external clock sources when available and falling back to TCXO when needed.
I need a precision in the µs range.
I'm more familiar with CPU than FPGA but I believe that for this application, a tiny FPGA will be more appropriated.
To your opinion, what will be the best approach: classical logic using counters and basic logic blocks, or a more smarter design using PLL?
Thank you
Regards