Why wide demux allows the partitioning of memory bandwidth to be able to change

[TONGSUSBU]

I have recently read an article, and one of the sentences said:
>
For example, the demux used in the read network has the ability to direct all of the read bandwidth to any of the read ports on any cycle. Such flexibility is useful in applications where the partitioning of memory bandwidth to read ports needs to change over time
>
I am wondering, why is this sentence true, and if possible, could u offer me some citations that suggesting this should be true? the original text is called "Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces"

I have tried to read some books regarding wide demux and memory bandwidth management on FPGA, yet nothing seems helpful. just give me some citations that is possible to answer this question would be enormously helpful to me!

[vstrakh]

That's weirdly formulated question.
The ability to redirect the read bandwidth between the ports is the property of the design of DRAM controller. Be it a demux or anything else - is irrelevant to the feature being wanted from the design, and whether it was a wide nor not-so-wide demux is also irrelevant - it will be exactly of the width required to implement the feature.
Why it allows? Because it was a wanted feature and the module in question was designed that way.

[TONGSUSBU]

I am really sorry that I asked such a bizarre question, I am really just an undergraduate and really a beginner of Computer Architecture or fpga. The original text is called "Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces", u can search it online if u want. What the article essentially said is that they think that wide-demux is overprovisioned in this design and they optimize it by changing wide-demux to shifter(rotation unit). The problem of the origin design (because the usage of demux) is that in each clock cycle one read port would use all of the bandwidth of the DRAM. now by changing wide demux to shifter, in each clock cycle, all read port from processors will  evenly use the bandwidth of DRAM, instead of one port per cycle.

[vstrakh]

You don't need to apologize, nothing wrong is done
They discuss the differences between their initial approach and the updated one. Some stuff was not really used to the full capacity, or there was no real cases for its use. So they've redesigned that portion, additionally achieving another improvement.
Your question felt weird because it sounds like you're assuming the "wide demux" has some inherent property of being capable to do something high-level, and the question was "why it does so". It doesn't, because it's not inherent feature of a demux in a general meaning. The demux is just something that happened to be in use in one very specific design, and that ability is there because of the design, not because of the demux.