poblems with capturing the sine wave in xilinx chipscope!

[javad2040]

Hi guys,
I designed a Data Acquisition system with ADS131e08 ADC and spartan6 FPGA.
I config the ADC and read data from it by my vhdl code that it contains several States. In this states, the ADC first reset and then the Config registers sets correctly.
I use xilinx Chipscope to capture the received data. when the Analog input of ADC is set to DC values, the received data in chipscope is correct and no problems, but when analog input connected to AC value(sine wave), the received data is not sine.
I set the ADC parameters to:
Fclk= 2.048 MHz
Fsclk = 18.432 MHz
Fchipscope= 2* Fsclk
Data Rates : 1KSPS
RESOLUTION = 24bit
AVDD = +2.5v
AVSS = -2.5v
sine Wave (peek to peek = 4v) that is less than the ADC Vp-p = AVDD - AVSS.

I guess the problem is related to the Chipscope settings?Rights?
Please help me to solve this problem.
regards,

[ali_asadzadeh]

javad2040 it would be way more helpful for us if you could share some codes or your chip-scope files

[iMo]

It may work provided your Gain=1 and the 4Vpp sine signal is centered at 0V.
The Signal_pp*Gain must fit into AVDD-0.3V .. AVSS+0.3V, afaik.

[javad2040]

Thank you for reply.

The ADC Registers are:

CONFIG1 = 0xD6 , CONFIG2 = 0xF0 , CONFIG3 = 0xC0
CH1SET = 0x10 , GAIN1 = 1 , MUX1 = 000 (normal input)
CHnSET = 0x90 , n = 2...8 this channel power downed
and
Fclk = 2.048 MHz
Fsclk = 18.432

I change the Fchipscope to new value that produced by this manner:
I use sine wave with frequency 50 Hz that period of it is 20ms. I sample the sine wave 256 times with ADC that total frequency is 256 x 50Hz. I produce this frequency by counter and send it to the Xilinx ChipScope and received data is semi-sine wave (below figure) and should be sine wave because of ADC resolution (24 bit).
I use oscilloscope to saw the sine wave that Vp-p of it is whole 4v that is safe and less than the ADC inputs Vp-p.

Please help me to find the problem and ADC capture the sine wave correctly.

best regards,