In principle, more chips + interleaving logic could have as much bandwidth as you want. But the logic needed to implement the interleaving would have to be fast and custom and therefore expensive. Also, the latency would be pretty bad. DDR5 isn't much lower latency than original SDRAM, but the intermediate logic would add significant latency that would be undesirable. Finally, the burst size would be a problem. To get the highest throughput from DRAM you need to burst. But if you take 8x older generation DRAM chips and mux them, your burst size per RAM would be 1/8th the size.
So overall I don't think you could make this work feasibly, even with custom silicon. There is a reason that DRAM still uses wide, parallel, single-ended data busses and is always clustered as tightly around the processor as packaging will allow.