Memory bank question?

[hap2001]

I've read that many old computer systems/processors are limited by the hardware address lines, so they can only have little amount of RAM+ROM.
And it's mentioned one way to workaround this is to use memory banking, but the computer still only see 1 rank at a time, and making use of total amount of memory (bank switching) is inefficient.
However I believe modern PCs usually have multiple banks of memory, and they just work like a whole thing seamlessly.
How do modern computers solve this problem, or did I misunderstood anything?

[xvr]

How do modern computers solve this problem, or did I misunderstood anything?

Bank of memory in modern computer has the same relationsip to the Bank of memory of old computer as it does to the Bank of a river. 
Memory bank of old computer is a space inside address space of CPU to which different parts of RAM could be mapped.
Memory bank in modern computer is a socket for physical memory chip (or chips). And you can populate these banks with physical memory. All populated memory comprises unified address space for CPU (there is no any separation inside it).

PS. NUMA architecture of modern computers is out of scope of this description 

[David Hess]

I've read that many old computer systems/processors are limited by the hardware address lines, so they can only have little amount of RAM+ROM.
And it's mentioned one way to workaround this is to use memory banking, but the computer still only see 1 rank at a time, and making use of total amount of memory (bank switching) is inefficient.

That is referred to as "bank switching".  IBM PC style computers had various forms of bank switching which could later be emulated with the paged memory management features of the 386 and later processors.

However I believe modern PCs usually have multiple banks of memory, and they just work like a whole thing seamlessly.
How do modern computers solve this problem, or did I misunderstood anything?

Modern processors either have enough address lines, or decode some of the address lines into bank select outputs making things easier.  For instance 3 address lines may be decoded into 8 bank selects using a 3-to-8 decoder.  Processors that support multiple memory channels are doing this internally but multiple memory channels may be accessed simultaneously while banks can only be accessed one at a time.

[m k]

Accessing memory is a chain of operations.

Accessing DRAM is a longer chain, things like CS, OE, RAS, CAS and R/W must be maintained.

With static RAM it can be just OE and R/W.
Means that all chips are accessed, but only one has its output enabled.

With memory controller in between the access can be piped, the controller can store different links of a chain.
CPU could do it also of course but more pins are needed and with extra controller optimizing clocks are easier.

[jzx]

The bank switching was used mainly by 8 bit computers, with a limitation of 64k  .
When the 6502, 8080 etc were designed, 64k was science fiction,  very big, very expensive, nobody needed so many k, but later  memory lowered its price, programs growt, and you know.

Bank switching was used with some 16 bits systems, as the pc, but no so commonly as with 8 bit systems. Later processors normally have  enough adressing lines to not use bank switching.

In modern computers, normally have more than one adress bus and can control more than one "memory" at same time, those are the modern banks. Doing this the processor can use the memory banks faster than if they where in the same bus, but for the program there is no difference. Because of this normally is better to fill all the banks, a bit faster, although with caches today the difference can be small.

[SiliconWizard]

Well, in 16-bit real mode, x86 with its segmented memory access behaves essentially as one with "memory banking". It's just that segment registers are a whole part of the instruction set, so "much" more efficient than tricks used for 8-bit systems.

Also, with the 8088/8086 and their limited address space (1MB), there were memory extensions that also acted like memory banks, and this "extended" memory was also cumbersome to access.

With "modern" CPUs, it's getting pretty hard to run into the limit of even their external address bus. But they also implement MMUs (usually), which do a lot of tricks "transparently" as well. Oh and DRAM has become a bottleneck for a rather long time now too, so caches always sit in between, providing another layer between actual system RAM and CPUs.

[Whales]

Modern desktop processors have:

1) MMUs (memory management units)
2) A crazily big address space (something like 48 bits.  The full 64 bits are not used in practice, I think)

MMUs do lots of what you might call bank switching (but it's not called that any more).  Physical peripherals (like RAM and PCIE cards) are mapped to arbitrary address ranges in memory.  The MMU can do more fun too.

The address space isn't 64 bits (yet) on a 64-bit desktop processor.  There is no point, even 48 bits is more than 250 terabytes (you could try to memory map your whole harddrive many times over).  For example I'm writing this on a Intel i5-6300U which reports:

address sizes   : 39 bits physical, 48 bits virtual

[jzx]

Also, with the 8088/8086 and their limited address space (1MB), there were memory extensions that also acted like memory banks, and this "extended" memory was also cumbersome to access.

This was https://en.wikipedia.org/wiki/Expanded_memory#EMS . At first this was an expansion card and later was emulated by EMM386 in MSDOS.

[hap2001]

Thank you everyone, I think I understand it more.