Wien Bridge project

[richlooker]

How about digitally ?

That kinda defeats the purpose. For me this is more a research project than a practical one. I specifically want to use a wien bridge oscillator, hoping I will learn something along the way, and IMHO the digital domain is lifeless and boring. ANyone can hook up an Arduino and load a program from a website, but where's the fun in that?

Cheers, Richard

[richlooker]

I was just reading in "Timer/Generator Circuits Manual" by R.M. Marston that the bounce problem of variable Wien circuits can be minimized with diode stabilization (two diodes in anti-parallel in the feedback path).  See page 19.  Can also be done with back-to-back Zeners (page 20).

Definitely, yes. And, as the feedback is non-linear, it also introduces more distortion than any of the linear VGC methods.

Richard

[Vovk_Z]

the linear VGC methods.

- Hm? 

[richlooker]

the linear VGC methods.

- Hm? 

I know, not really linear as in linear, but with a time constant that makes them behave linear or near-linear at the oscillator frequency; a filament lamp, FET or optocoupler will stabilize amplitude based on averaged amplitude, while diodes will stabilize based on immediate amplitude, ie. for each positive or negative peak.

[David Hess]

The incandescent lamp has been replaced by optocouplers and balanced FETs in some designs.

There is a tricky compromise in the gain control.  The common Wien bridge has one side grounded which grounds one side of the gain control element simplifying things.  But when common mode suppression is added to the Wein bridge which eliminates the distortion caused by limited common mode rejection of the amplifier, the gain control element is no longer grounded and must be floating which is easy to do with an incandescent lamp or optocoupler but not so easy with FETs.

There *are* ways to make a balanced FET gain control but I have never seen them used with a Wien bridge so it may be worth looking into if you want to do something new.  Take a look at schematic 7 of the Tektronix 7D20 for an example of a balanced JFET gain control; it uses a dual JFET because its control is open loop but a closed loop control only requires a single JFET.

The better alternative now is to use a VCA as shown in the oscillator designed by Dale Eagar which can be found on page 26 of Linear Technology Magazine of February 1994 where he uses an LT1228 transconductance amplifier.  If you do not want the ultimate of performance using his design, then adapt the LT1228 gain control to a simpler design without the "super" gain blocks.  This is what I would do.

[Conrad Hoffman]

One should also be aware of the vacuum thermistors used for gain control in the GR and various other oscillators. They were a tiny spec of thermistor in an evacuated glass tube, which allowed them to run hot with minimum power. Great device but AFAIK, no longer in production.
http://electrojumble.org.uk/DATA/STC_B_&_R_Thermistors.pdf

[richlooker]

The better alternative now is to use a VCA as shown in the oscillator designed by Dale Eagar which can be found on page 26 of Linear Technology Magazine of February 1994 where he uses an LT1228 transconductance amplifier.  If you do not want the ultimate of performance using his design, then adapt the LT1228 gain control to a simpler design without the "super" gain blocks.  This is what I would do.

Code: [Select]

An Ultra-Low-Distortion,
10kHz Sine-Wave Source for
Calibration of 16-Bit or
Higher Analog-to-Digital
Converters
There has now been posted > 10 suggestions for low-distortion oscillators, but not one of them are designed for operation over four decades, as is my requirement.

Cheers, Richard

[T3sl4co1l]

I suspect that, given:
- Enough OTAs
- Enough decks of switches
- Enough ganged potentiometers

You've listed / seen enough designs that, I suspect, given the above -- such is possible.  All that's left is, y'know, "draw the rest of the fucking owl" as the meme says.   As I mentioned earlier -- such is the realm of the highly-optimized classic-HP design, and there's really not much to substitute for that -- given that digital solutions are specifically excluded!  You've seen a number of designs, of varying complexity, that handle their (necessary, as noted from a theoretical basis) nonlinearities, in various ways, time-dependent or not; with consequential compromises in distortion and settling.  These are designs in vary degrees of completeness, for various purposes; to make a truly general purpose unit, plenty of work will be required, doing all that refinement and optimization.  Free lunches and all that.

Tim

[richlooker]

There are three distinct problems for me to tackle;

• A basic oscillator with inherent bandwidth high enough that a given resistor value of the RC element will yield close enough to the theoretical frequencies with the four different capacitor values (1µF-100nF-10nF-1nF)
• A gain control element which introduces minimal distortion
• An amplitude-to-DC converter with fast and frequency-independent settling time

I will concentrate on the latter for now, and I have decided to stick with the sample&hold peak detector concept until either I'm satisfied or I have to conclude it's not feasible. As I wrote in the initial post, there are a number of shortcomings with the design suggested at sound-au.com, and I have tried to address these.

COmponent designations in the following description refers to the original diagram, from this article: https://sound-au.com/project174.htm

• The diode D2 introduces a voltage drop, unavoidable with this circuit topology, but I have replaced the basic diode with a Schottky to reduce the voltage drop
• The antiparallel diodes D2/D3 are supposed to let C9 hold the peak for a while, until D3 starts to conduct and C9 discharges, tracking the input voltage. This means there is a small and frequency-dependent time window where the sampling has to occur, and it also means the further circuitry has to handle both positive and negative voltages. I have removed D3, and instead added a comparator that, as the input signal falling edge crosses zero, opens a JFET that discharges the capacitor. This capacitor is shorted by the JFET for the entire negative half wave
• The buffer JFET Q1 is nonlinear in this configuration, and DC across R15 restricts the input voltage tracking range. The secondary comparator U2B shorts the hold capacitor C11 through Q3when the input peak is below a given level to compensate for this; I have replaced the single JFET buffer with a JFET input opamp, making the comparator/transistor arrangement redundant. This also helps with droop, as C11 would discharge through CE leakage current in Q3
• The LM2903 comparators are too slow for operation at 100kHz; I have replaced them with LM311P which has a response time of ~150nS
• The peak tracking capacitor C9 is connected directly to the input of comparator U3A, increasing droop; I have introduced a JFET input opamp between these

This is my modified/enhanced circuit:



The VM/AM meters are there for transient analysis; I will shortly post my results.

Cheers, Richard

[richlooker]

- Enough OTAs
- Enough decks of switches
- Enough ganged potentiometers

I will employ plenty of decked switches. One challenge I have to overcome is I need to make a three-deck/6-pole 4-position switch out of two dual-deck/four-pole ones.

Ganged potmeters are out of the question; if such ones with the needed precision even exists, I'm sure they are way beyond my budget. I have a dual-deck 26-position rotary switch I will fit with a resistor ladder to get 25 discrete frequencies per decade - for now I have calculated the values and prepared resistors to get (for the second decade) 100, 110, 120, 130, 145, 160, 175, 190, 210, 230, 250, 275, 300, 330, 360, 400, 440, 480, 525, 575, 630, 690, 760, 830 and 910 Hz +/- 0.075% (theoretically)

Cheers, Richard

[richlooker]

I have established that, in order to keep settling time fairly independent of frequency, I need different values of the sample pulse timing capacitor C2 for each decade. Here are the waveforms with a 1kHz signal and C2 at 10nF.



The sampling switch T2 exhibits a couple of anomalies I don't understand;

• It has a voltage drop drain-source of about 0.3-0.4 V - not a big deal considering I'm not that concerned with the absolute value of the peaks, but can it be avoided?
• During sampling, Rds must be as low as possible, so Vgs has to be 0V or slightly higher. As both drain and source are floating, the voltage at source is not known, so I just have to ensure that Vgs is high enough. This means the base-substrate diode will be forward biased and start to conduct, this leads to a current that contributes to the capacitor charge, shown as the little peak on VM4. What I don't understand is that it discharges again when the sampling pulse VM3 falls, how can this be?

Cheers, Richard

[T3sl4co1l]

Usual way to drive JFETs is to pullup gate to source.  The enhancement going to positive Vgs isn't substantial, and if you need lower Rds(on) just choose a bigger JFET.

Kind of related: JFETs should possibly behave as UJTs, i.e. enhancing significantly under charge injection (forward gate bias).  I haven't observed any significant effect in switching JFETs -- perhaps UJTs have much lower doping, and much longer base length, exaggerating the effect?

With a J110, Rds(on) shouldn't be a problem.  The max 85pF Cg(on) is a pretty big fraction of 1nF though.  Perhaps a smaller one would perform better.

May also find better results (less charge injection) using balanced CMOS switches.

Tim

[richlooker]

Usual way to drive JFETs is to pullup gate to source.  The enhancement going to positive Vgs isn't substantial, and if you need lower Rds(on) just choose a bigger JFET.

I know, but there is no way to pullup gate to source, or maybe - can I use the output of U6 in some way? Maybe through an analog switch?

With a J110, Rds(on) shouldn't be a problem.  The max 85pF Cg(on) is a pretty big fraction of 1nF though.  Perhaps a smaller one would perform better.

You mean a JFET with lower Cg(on)? Suggestions?

May also find better results (less charge injection) using balanced CMOS switches.

I have considered this, but that will require higher gate voltage, ie. minimum Rds for a MOSFET requires Vgs > 4V, right?


/Richard

[T3sl4co1l]

Usual way to drive JFETs is to pullup gate to source.  The enhancement going to positive Vgs isn't substantial, and if you need lower Rds(on) just choose a bigger JFET.

I know, but there is no way to pullup gate to source, or maybe - can I use the output of U6 in some way? Maybe through an analog switch?

Pull to the low impedance: T1 to ground, T2 to U1b output.

I wonder what LM311 output capacitance is, or in general how its output switching depends on load current and capacitance.  Its output capacitance isn't specified.  D3 probably isn't useful in the end, but I wonder if a cascode would be (e.g. a 2N3904 with R + 2 x diodes voltage divider for base bias, maybe with a Baker clamp as well).  In other words, keep the LM311 output voltage swing small, assuming its current swings faster.  It can also be biased up to run at higher current (mind to put in a voltage limit so it doesn't pull the 3904's emitter into breakdown).

As for generally faster comparators, I don't have a good recommendation offhand; the next faster option in my box is MCP6561 which is 5V max (and CMOS output).  I'm sure there is something available; I do recall there's a big gap between classic parts (~100s ns response time) and fast ones (<10ns), just don't be alarmed if it happens to be far faster than you expected.

You mean a JFET with lower Cg(on)? Suggestions?

Well, J112 and friends, kind of the next step down I guess; PN4391 similar; or the few remaining RF JFETs (be careful not to make them oscillate ) with Rds(on) around there.  2N5486 might be on the small side, BF862 (or its newer replacement CPH3910) is probably about right.

Rds(on) far below 100 ohms doesn't seem all that useful, as the TL072 isn't capable of much more current than an equivalent resistance around there.  For T2 at least.

I think the required sample window (essentially 3*Rds(on)*Csample, say) versus charge injection (ΔVg * Cg(on) / Csample) is a roughly constant amount.  There isn't much performance difference among JFETs, it's mainly about how wide the channel is; and a wider channel has proportionally more capacitance and less resistance.  The main difference is in fine optimizations, matching channel width to circuit impedance (hence ~100s ohms or ~10s mS parts are most practical at RF), and how much extra capacitance comes from wiring/pad connects, I think.

I have considered this, but that will require higher gate voltage, ie. minimum Rds for a MOSFET requires Vgs > 4V, right?

Yes, well you have +/-9V supplies so that's no problem at all.   DG401, DG612, TC4W66FU, even the bog standard 4066 may do.

CMOS switches work over the full supply range.  At low voltages (near VSS), the NMOS is doing the work, at high voltages (near VDD) the PMOS.  There is an peak in the middle, in Rds(on), particularly exaggerated at low supply voltages -- IC MOS are more like Vgs(th) = 1-2V, so for supply voltages around twice that, they stop working (Rds(on) just too high at middle voltages).  At 18V supplies, Rds(on) will be pretty stable, and as low as it gets for most parts.

Tim

[MikeK]

This project is on my to-do list.  Uses an LED/photoresistor for gain control.  Claims low THD.  Perhaps it could be expanded to include your needed range?

http://redcircuits.com/Page82.htm

[richlooker]

Sampling pulse timing capacitor per frequency decade:

• 10Hz-100Hz: 100nF
• 100Hz - 1kHz: 10nF
• 1kHz - 10kHz: 1nF
• 10kHz - 100kHz: 100pF

A close look at T2 gate current, sampling pulse and output voltage at 10kHz, C2=1nF:



For some reason there is a small "pre-pulse." The positive gate current inrush is probably insignificant, but the reverse current flowing out from the gate when Vgs goes negative approaches 60mA, I assume this is the source-gate on-capacitance (J110: max 85pF) discharging.

/Richard

[richlooker]

Increasing the hold capacitor C3 to 10nF all but eliminates the ripple on the output voltage. In the original design, this capacitor is 100nF; I reduced it in an attempt to make do with a single C2 value across the entire frequency range, and I could bring it down to 1nF without droop as I removed the "output shorting" BJT, but 10nF should be OK and still give fast settling times.

[richlooker]

At 100kHz, C2=100pF, things are getting problematic. U1a gets current limited, making the positive half triangle-shaped. The sampling pulse does not get high enough, limiting Vout to just above 4V.

(I put meaningful names on the curves; Tina-TI sorts them alphabetically so i named Vout "Vvout" to make it appear last 



Scope display of the same:

[richlooker]

Reducing R6 to 10k fixes that, and also fixes the voltage drop over T2. Now I wonder if R5 and D3 fill any purpose at all; will try without them.

I am a little worried about the 75mA T2 Ig spikes, whether this may damage the JFET.



/Richard

[richlooker]

Using an LM6171B as input amp fixed the current limiting. Happy with the design for now; time to breadboard and do real tests.

[richlooker]

I had to do a couple final simulations before building the circuit.

First, verifying that it performs well at lower frequencies. In all instances Vout settles at the first peak, and peak voltage tracking is spot on. Iout U1a shows a ~60µA spike at the input signal zero crossing, indicating that T1 shorts C1 while D1 is still conducting. I'll pull the + input of comparator U2 one schottky drop below ground to avoid that.

100Hz, C2=10nF:


100Hz, C2=100nF:


10Hz, C2=100nF:


/Richard

[richlooker]

Finally a closer look at the currents flowing through T2.

This simulation is at 10kHz with C2=1nF. The three upper waveforms are currents where the positive direction is inwards to the JFET, and the fourth one is the sum of these. Interesting that the sum stays within +5/-4 pA, indicating that any charges are the same after the Ig peak as before it. It also seems Idrain i current-limited by U1b. Would be interesting to see what happens if I replace U1b as well with an LM6172; maybe Idrain - and thereby also the little Vout drop - will be reduced. I won't find out before I receive my order of LM6171/6172 from mouser, as Tina-TI reports a convergence problem with LM6171/6172 instead of TL072.



/Richard

[richlooker]

Modified sample&hold peak detector breadboarded, ready for testing. For now it's using TL072 until I get my LM6172s, meaning it's not very usable beyond 20-30kHz.

[richlooker]

I got the simulation / transient analysis working with LM6172 for both U1a and U1b. TL072 output impedance was clearly a limiting factor. Now it's wickedly fast - this is at 100kHz; peak voltage tracked (minus 300mV schottky drop) after first peak 

I can recommend LM6171/6172 from TI. I have have used these with success.

 - this really did the trick (in simulation, at least) and they're not crazy expensive either; thanks again 

And here is the final schematic:



Testing and scoping tomorrow.

/Richard

[T3sl4co1l]

Nice!

I wonder if it would be worthwhile, to add another op-amp to assist the schottky?  It's clearly the weak link, as a tempco offset.

I think the approach would be... wire U1a as a precision rectifier, but not actually because its buffered (well, amplified too) signal is needed elsewhere -- so it would add another op-amp.  Also, it needs to be rather fast slewing (even with the diode-from-output-to-input clamping trick).

It would be nice to not discharge C1 all the way as well, both giving U1a (or the precision recitifier) an easier time and reducing required voltage changes; I'm not sure exactly how to do that here.  It would be nice if the peak can be sensed by comparator, without having to differentiate it (which would likely add yet another wafer to the switch).

I mean, you're already differentiating it, that's effectively what U3 is doing -- which means that might be a good section to investigate further.  Specifically, D1 leakage is the limiting factor, and C1 reactance rises at low frequencies so noise goes up as well, which introduces phase noise which I guess puts a bit of variance on the output (earlier/later sampling results in an incrementally lower voltage, either during the rising edge before C1's voltage has reached peak, or the falling edge as C1 discharges into leakages?).

I suppose that's another nice thing about quadrature, you have zero and peak crossings available implicitly.  Wonder if any node, or branch [current], in the Wien bridge does?  I'd have to think about it..

Tim